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公开(公告)号：US07981756B2
公开(公告)日：2011-07-19
申请号：US12317656
申请日：2008-12-22
申请人： Nick Lindert , Brian Doyle , Dinesh Somasekhar , Christopher J. Jezewski , Swaminathan Sivakumar , Kevin Zhang , Stephen Wu
发明人： Nick Lindert , Brian Doyle , Dinesh Somasekhar , Christopher J. Jezewski , Swaminathan Sivakumar , Kevin Zhang , Stephen Wu
IPC分类号： H01L21/20
CPC分类号： H01L27/101 , H01L28/90
摘要： A process of forming a semiconductive capacitor device for a memory circuit includes forming a first capacitor cell recess and a second capacitor cell recess that are spaced apart by a capacitor cell boundary of a first height. The process includes lowering the first height of the capacitor cell boundary to a second height. A common plate capacitor bridges between the first recess and the second recess over the boundary above the second height and below the first height.
摘要翻译： 形成用于存储电路的半导体电容器器件的工艺包括形成由第一高度的电容器单元边界隔开的第一电容器单元凹槽和第二电容器单元凹槽。 该过程包括将电容器单元边界的第一高度降低到第二高度。 普通的平板电容器在第一凹槽和第二凹槽之间跨过第二高度并低于第一高度的边界。
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公开(公告)号：US20100155887A1
公开(公告)日：2010-06-24
申请号：US12317656
申请日：2008-12-22
申请人： Nick Lindert , Brian Doyle , Dinesh Somasekhar , Christopher J. Jezewski , Swaminathan Sivakumar , Kevin Zhang , Stephen Wu
发明人： Nick Lindert , Brian Doyle , Dinesh Somasekhar , Christopher J. Jezewski , Swaminathan Sivakumar , Kevin Zhang , Stephen Wu
CPC分类号： H01L27/101 , H01L28/90
摘要： A process of forming a semiconductive capacitor device for a memory circuit includes forming a first capacitor cell recess and a second capacitor cell recess that are spaced apart by a capacitor cell boundary of a first height. The process includes lowering the first height of the capacitor cell boundary to a second height. A common plate capacitor bridges between the first recess and the second recess over the boundary above the second height and below the first height.
摘要翻译： 形成用于存储电路的半导体电容器器件的工艺包括形成由第一高度的电容器单元边界隔开的第一电容器单元凹槽和第二电容器单元凹槽。 该过程包括将电容器单元边界的第一高度降低到第二高度。 普通的平板电容器在第一凹槽和第二凹槽之间跨过第二高度并低于第一高度的边界。
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公开(公告)号：US08519462B2
公开(公告)日：2013-08-27
申请号：US13169864
申请日：2011-06-27
申请人： Yih Wang , M. Clair Webb , Nick Lindert , Swaminathan Sivakumar , Kevin X. Zhang , Dinesh Somasekhar
发明人： Yih Wang , M. Clair Webb , Nick Lindert , Swaminathan Sivakumar , Kevin X. Zhang , Dinesh Somasekhar
IPC分类号： H01L27/108
CPC分类号： H01L27/10814 , H01L27/0207 , H01L27/10891
摘要： A 6F2 DRAM cell with paired cells is described. In one embodiment the cell pairs are separated by n-type isolation transistors having gates defining dummy word lines. The dummy word lines are fabricated from a metal with a work function favoring p-channel devices.
摘要翻译： 描述了具有成对单元的6F2 DRAM单元。 在一个实施例中，单元对由具有限定虚拟字线的门的n型隔离晶体管分开。 虚拟字线由具有有利于p沟道器件的功函数的金属制成。
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公开(公告)号：US20120326218A1
公开(公告)日：2012-12-27
申请号：US13169864
申请日：2011-06-27
申请人： Yih Wang , M. Clair Webb , Nick Lindert , Swaminathan Sivakumar , Kevin X. Zhang , Dinesh Somasekhar
发明人： Yih Wang , M. Clair Webb , Nick Lindert , Swaminathan Sivakumar , Kevin X. Zhang , Dinesh Somasekhar
IPC分类号： H01L27/108
CPC分类号： H01L27/10814 , H01L27/0207 , H01L27/10891
摘要： A 6F2 DRAM cell with paired cells is described. In one embodiment the cell pairs are separated by n-type isolation transistors having gates defining dummy word lines. The dummy word lines are fabricated from a metal with a work function favoring p-channel devices.
摘要翻译： 描述了具有成对单元的6F2 DRAM单元。 在一个实施例中，单元对由具有限定虚拟字线的门的n型隔离晶体管分开。 虚拟字线由具有有利于p沟道器件的功函数的金属制成。
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5.发明授权Method of patterning a metal on a vertical sidewall of an excavated feature, method of forming an embedded MIM capacitor using same, and embedded memory device produced thereby 有权在挖掘特征的垂直侧壁上图案化金属的方法，使用其形成嵌入式MIM电容器的方法以及由此产生的嵌入式存储器件公开(公告)号：US07927959B2
公开(公告)日：2011-04-19
申请号：US12286338
申请日：2008-09-30
申请人： Steven J. Keating , Nick Lindert , Nadia Rahhal-Orabi , Brian Doyle , Satyarth Suri , Swaminathan Sivakumar , Lana Jong , Lin Sha
发明人： Steven J. Keating , Nick Lindert , Nadia Rahhal-Orabi , Brian Doyle , Satyarth Suri , Swaminathan Sivakumar , Lana Jong , Lin Sha
IPC分类号： H01L21/467
CPC分类号： H01L28/40 , H01G4/012 , H01G4/33 , H01L23/5223 , H01L27/10852 , H01L28/90 , H01L28/91 , H01L28/92 , H01L2924/0002 , H01L2924/00
摘要： A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.
摘要翻译： 在挖掘特征（130,330,830）的垂直侧壁（132,332,832）上图案化金属（141,341,841）的方法包括将材料（350）放置在挖掘的特征中，使得部分 （435）暴露在材料上方的挖掘特征中，使用第一湿蚀刻化学法将金属的暴露部分从垂直侧壁上蚀刻出来，并且通过使用第二湿蚀刻化学法将其去除，从挖掘的特征中去除材料 湿蚀刻化学。 所描述的方法可以用于产生适合于eDRAM器件的MIM电容器（800）。
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6.发明申请METHOD OF PATTERNING A METAL ON A VERTICAL SIDEWALL OF AN EXCAVATED FEATURE, METHOD OF FORMING AN EMBEDDED MIM CAPACITOR USING SAME, AND EMBEDDED MEMORY DEVICE PRODUCED THEREBY 有权在金属切割特征的垂直平面上绘制金属的方法，使用其形成嵌入式MIM电容器的方法以及生产的嵌入式存储器件公开(公告)号：US20130234290A1
公开(公告)日：2013-09-12
申请号：US13868273
申请日：2013-04-23
申请人： Steven Keating , Nick Lindert , Nadia Rahhal-Orabi , Brian Doyle , Satyarth Suri , Swaminathan Sivakumar , Lana Jong , Lin Sha
发明人： Steven Keating , Nick Lindert , Nadia Rahhal-Orabi , Brian Doyle , Satyarth Suri , Swaminathan Sivakumar , Lana Jong , Lin Sha
IPC分类号： H01L49/02
CPC分类号： H01L28/40 , H01G4/012 , H01G4/33 , H01L23/5223 , H01L27/10852 , H01L28/90 , H01L28/91 , H01L28/92 , H01L2924/0002 , H01L2924/00
摘要： A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.
摘要翻译： 在挖掘特征（130,330,830）的垂直侧壁（132,332,832）上图案化金属（141,341,841）的方法包括将材料（350）放置在挖掘的特征中，使得部分 （435）暴露在材料上方的挖掘特征中，使用第一湿蚀刻化学法将金属的暴露部分从垂直侧壁上蚀刻出来，并且通过使用第二湿蚀刻化学法将其去除，从挖掘的特征中去除材料 湿蚀刻化学。 所描述的方法可以用于产生适合于eDRAM器件的MIM电容器（800）。
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公开(公告)号：US08441057B2
公开(公告)日：2013-05-14
申请号：US13028400
申请日：2011-02-16
申请人： Steven J. Keating , Nick Lindert , Nadia Rahhal-Orabi , Brian Doyle , Satyarth Suri , Swaminathan Sivakumar , Lana Jong , Lin Sha
发明人： Steven J. Keating , Nick Lindert , Nadia Rahhal-Orabi , Brian Doyle , Satyarth Suri , Swaminathan Sivakumar , Lana Jong , Lin Sha
IPC分类号： H01L29/92
CPC分类号： H01L28/40 , H01G4/012 , H01G4/33 , H01L23/5223 , H01L27/10852 , H01L28/90 , H01L28/91 , H01L28/92 , H01L2924/0002 , H01L2924/00
摘要： A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.
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8.发明申请METHOD OF PATTERNING A METAL ON A VERTICAL SIDEWALL OF AN EXCAVATED FEATURE, METHOD OF FORMING AN EMBEDDED MIM CAPACITOR USING SAME, AND EMBEDDED MEMORY DEVICE PRODUCED THEREBY 有权在金属切割特征的垂直平面上绘制金属的方法，使用其形成嵌入式MIM电容器的方法以及生产的嵌入式存储器件公开(公告)号：US20110134583A1
公开(公告)日：2011-06-09
申请号：US13028400
申请日：2011-02-16
申请人： Steve J. Keating , Nick Lindert , Nadia Rahhal-Orabi , Brian Doyle , Satyarth Suri , Swaminathan Sivakumar , Lana Jong , Lin Sha
发明人： Steve J. Keating , Nick Lindert , Nadia Rahhal-Orabi , Brian Doyle , Satyarth Suri , Swaminathan Sivakumar , Lana Jong , Lin Sha
IPC分类号： H01G4/00
CPC分类号： H01L28/40 , H01G4/012 , H01G4/33 , H01L23/5223 , H01L27/10852 , H01L28/90 , H01L28/91 , H01L28/92 , H01L2924/0002 , H01L2924/00
摘要： A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.
摘要翻译： 在挖掘特征（130,330,830）的垂直侧壁（132,332,832）上图案化金属（141,341,841）的方法包括将材料（350）放置在挖掘的特征中，使得部分 （435）暴露在材料上方的挖掘特征中，使用第一湿蚀刻化学法将金属的暴露部分从垂直侧壁上蚀刻出来，并且通过使用第二湿蚀刻化学法将其去除，从挖掘的特征中去除材料 湿蚀刻化学。 所描述的方法可以用于产生适合于eDRAM器件的MIM电容器（800）。
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9.发明申请Method of patterning a metal on a vertical sidewall of an excavated feature, method of forming an embedded MIM capacitor using same, and embedded memory device produced thereby 有权在挖掘特征的垂直侧壁上图案化金属的方法，使用其形成嵌入式MIM电容器的方法以及由此产生的嵌入式存储器件公开(公告)号：US20100079924A1
公开(公告)日：2010-04-01
申请号：US12286338
申请日：2008-09-30
申请人： Steven J. Keating , Nick Lindert , Nadia Rahhal-Orabi , Brian Doyle , Satyarth Suri , Swaminathan Sivakumar , Lana Jong , Lin Sha
发明人： Steven J. Keating , Nick Lindert , Nadia Rahhal-Orabi , Brian Doyle , Satyarth Suri , Swaminathan Sivakumar , Lana Jong , Lin Sha
IPC分类号： H01G4/008 , H01L21/311 , H01L21/20
CPC分类号： H01L28/40 , H01G4/012 , H01G4/33 , H01L23/5223 , H01L27/10852 , H01L28/90 , H01L28/91 , H01L28/92 , H01L2924/0002 , H01L2924/00
摘要： A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.
摘要翻译： 在挖掘特征（130,330,830）的垂直侧壁（132,332,832）上图案化金属（141,341,841）的方法包括将材料（350）放置在挖掘的特征中，使得部分 （435）暴露在材料上方的挖掘特征中，使用第一湿蚀刻化学法将金属的暴露部分从垂直侧壁上蚀刻出来，并且通过使用第二湿蚀刻化学法将其去除，从挖掘的特征中去除材料 湿蚀刻化学。 所描述的方法可以用于产生适合于eDRAM器件的MIM电容器（800）。
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10.发明申请EXPOSURE ACTIVATED CHEMICALLY AMPLIFIED DIRECTED SELF-ASSEMBLY (DSA) FOR BACK END OF LINE (BEOL) PATTERN CUTTING AND PLUGGING 有权用于线后退（BEOL）图案切割和插入的接触激活化学引导的自组装（DSA）公开(公告)号：US20150093702A1
公开(公告)日：2015-04-02
申请号：US14039140
申请日：2013-09-27
IPC分类号： H01L21/768 , G03F7/039 , H01L21/027
CPC分类号： G03F7/0392 , B81C1/00428 , B81C2201/0149 , G03F7/0002 , G03F7/0045 , G03F7/038 , G03F7/039 , G03F7/11 , G03F7/16 , G03F7/2004 , G03F7/2037 , G03F7/26 , H01L21/0337 , H01L21/31058 , H01L21/32 , H01L21/3205 , H01L21/32139 , H01L21/76816
摘要： Self-aligned via and plug patterning for back end of line (BEOL) interconnects are described. In an example, a structure for directed self-assembly includes a substrate and a block co-polymer structure disposed above the substrate. The block co-polymer structure has a polystyrene (PS) component and a polymethyl methacrylate (PMMA) component. One of the PS component or the PMMA component is photosensitive.
摘要翻译： 描述了用于后端（BEOL）互连的自对准通孔和插头图案。 在一个示例中，用于定向自组装的结构包括设置在衬底上方的衬底和嵌段共聚物结构。 嵌段共聚物结构具有聚苯乙烯（PS）组分和聚甲基丙烯酸甲酯（PMMA）组分。 PS组件或PMMA组件之一是光敏的。
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