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1.发明申请EXPOSURE ACTIVATED CHEMICALLY AMPLIFIED DIRECTED SELF-ASSEMBLY (DSA) FOR BACK END OF LINE (BEOL) PATTERN CUTTING AND PLUGGING 有权用于线后退（BEOL）图案切割和插入的接触激活化学引导的自组装（DSA）公开(公告)号：US20150093702A1
公开(公告)日：2015-04-02
申请号：US14039140
申请日：2013-09-27
IPC分类号： H01L21/768 , G03F7/039 , H01L21/027
CPC分类号： G03F7/0392 , B81C1/00428 , B81C2201/0149 , G03F7/0002 , G03F7/0045 , G03F7/038 , G03F7/039 , G03F7/11 , G03F7/16 , G03F7/2004 , G03F7/2037 , G03F7/26 , H01L21/0337 , H01L21/31058 , H01L21/32 , H01L21/3205 , H01L21/32139 , H01L21/76816
摘要： Self-aligned via and plug patterning for back end of line (BEOL) interconnects are described. In an example, a structure for directed self-assembly includes a substrate and a block co-polymer structure disposed above the substrate. The block co-polymer structure has a polystyrene (PS) component and a polymethyl methacrylate (PMMA) component. One of the PS component or the PMMA component is photosensitive.
摘要翻译： 描述了用于后端（BEOL）互连的自对准通孔和插头图案。 在一个示例中，用于定向自组装的结构包括设置在衬底上方的衬底和嵌段共聚物结构。 嵌段共聚物结构具有聚苯乙烯（PS）组分和聚甲基丙烯酸甲酯（PMMA）组分。 PS组件或PMMA组件之一是光敏的。
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公开(公告)号：US09625815B2
公开(公告)日：2017-04-18
申请号：US14039140
申请日：2013-09-27
IPC分类号： H01L21/768 , H01L21/027 , G03F7/039 , H01L21/033 , H01L21/3105 , H01L21/32 , G03F7/00
CPC分类号： G03F7/0392 , B81C1/00428 , B81C2201/0149 , G03F7/0002 , G03F7/0045 , G03F7/038 , G03F7/039 , G03F7/11 , G03F7/16 , G03F7/2004 , G03F7/2037 , G03F7/26 , H01L21/0337 , H01L21/31058 , H01L21/32 , H01L21/3205 , H01L21/32139 , H01L21/76816
摘要： Self-aligned via and plug patterning for back end of line (BEOL) interconnects are described. In an example, a structure for directed self-assembly includes a substrate and a block co-polymer structure disposed above the substrate. The block co-polymer structure has a polystyrene (PS) component and a polymethyl methacrylate (PMMA) component. One of the PS component or the PMMA component is photosensitive.
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3.发明授权Patterning of vertical nanowire transistor channel and gate with directed self assembly 有权垂直纳米线晶体管沟道和栅极的定向自组装图案化公开(公告)号：US09054215B2
公开(公告)日：2015-06-09
申请号：US13719113
申请日：2012-12-18
IPC分类号： H01L21/8234 , H01L29/78 , H01L29/775 , H01L29/66 , B82Y10/00 , B82Y40/00 , H01L29/423 , H01L29/06 , H01L29/16
CPC分类号： H01L21/823487 , B82Y10/00 , B82Y40/00 , H01L21/02532 , H01L21/02603 , H01L21/02642 , H01L21/28123 , H01L21/30625 , H01L21/823412 , H01L21/823418 , H01L21/823437 , H01L27/088 , H01L29/0676 , H01L29/16 , H01L29/42376 , H01L29/42392 , H01L29/517 , H01L29/66666 , H01L29/66742 , H01L29/775 , H01L29/7827 , H01L29/78618 , H01L29/78642 , H01L29/78651 , H01L29/78684 , H01L29/78696
摘要： Directed self-assembly (DSA) material, or di-block co-polymer, to pattern features that ultimately define a channel region a gate electrode of a vertical nanowire transistor, potentially based on one lithographic operation. In embodiments, DSA material is confined within a guide opening patterned using convention lithography. In embodiments, channel regions and gate electrode materials are aligned to edges of segregated regions within the DSA material.
摘要翻译： 定向自组装（DSA）材料或二嵌段共聚物可能基于一个光刻操作来最终限定垂直纳米线晶体管的栅电极的通道区域的特征。 在实施例中，DSA材料被限制在使用常规光刻图案化的引导开口内。 在实施例中，沟道区域和栅电极材料与DSA材料内的分离区域的边缘对准。
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公开(公告)号：US09530688B2
公开(公告)日：2016-12-27
申请号：US14822865
申请日：2015-08-10
IPC分类号： H01L21/4763 , H01L21/768 , H01L23/522 , H01L21/033 , H01L21/311
CPC分类号： H01L21/76877 , H01L21/0337 , H01L21/31144 , H01L21/76811 , H01L21/76816 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method of an aspect includes forming an interconnect line etch opening in a hardmask layer. The hardmask layer is over a dielectric layer that has an interconnect line disposed therein. The interconnect line etch opening is formed aligned over the interconnect line. A block copolymer is introduced into the interconnect line etch opening. The block copolymer is assembled to form a plurality of assembled structures that are spaced along a length of the interconnect line etch opening. An assembled structure is directly aligned over the interconnect line that is disposed within the dielectric layer.
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公开(公告)号：US20140053117A1
公开(公告)日：2014-02-20
申请号：US13997565
申请日：2011-12-30
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G03F1/36 , G03F1/70 , G06F17/5068
摘要： Techniques are provided for determining how thick or how deep to make the phased regions of a lithography mask. One example embodiment provides a method that includes: providing first mask layout design including a first test set, and providing a second mask layout design including a second test set, wherein the second test set is larger than the first test set; simulating critical dimensions through focus of structures of interest in the first test set for a range of phase depths/thicknesses, and selecting an initial preferred mask phase depth/thickness based on results of the simulating; and generating a fast thick-mask model (FTM) at the initial preferred phase depth/thickness, and correcting the second test set of the second mask layout design using the FTM, thereby providing an optimized mask layout design. A mask having the optimized mask layout design may be implemented to give the optimum patterning.
摘要翻译： 提供了用于确定制造光刻掩模的相位区域的厚度或深度的技术。 一个示例性实施例提供了一种方法，其包括：提供包括第一测试集的第一掩模布局设计，以及提供包括第二测试集的第二掩模布局设计，其中所述第二测试集大于所述第一测试集; 通过针对一系列相位深度/厚度的第一测试集合中关注的结构的焦点来模拟关键尺寸，并且基于模拟结果选择初始优选的掩模相位深度/厚度; 并且以最初的优选相位深度/厚度生成快速厚掩模模型（FTM），并且使用FTM校正第二掩模布局设计的第二测试集，由此提供优化的掩模布局设计。 可以实施具有优化的掩模布局设计的掩模以给出最佳图案化。
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6.发明申请DIRECTED SELF ASSEMBLY OF BLOCK COPOLYMERS TO FORM VIAS ALIGNED WITH INTERCONNECTS 审中-公开方向自组装块状共聚物形成与互连对齐的VIAS公开(公告)号：US20150348839A1
公开(公告)日：2015-12-03
申请号：US14822865
申请日：2015-08-10
IPC分类号： H01L21/768 , H01L21/311 , H01L23/522 , H01L21/033
CPC分类号： H01L21/76877 , H01L21/0337 , H01L21/31144 , H01L21/76811 , H01L21/76816 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method of an aspect includes forming an interconnect line etch opening in a hardmask layer. The hardmask layer is over a dielectric layer that has an interconnect line disposed therein. The interconnect line etch opening is formed aligned over the interconnect line. A block copolymer is introduced into the interconnect line etch opening. The block copolymer is assembled to form a plurality of assembled structures that are spaced along a length of the interconnect line etch opening. An assembled structure is directly aligned over the interconnect line that is disposed within the dielectric layer.
摘要翻译： 一方面的方法包括在硬掩模层中形成互连线蚀刻开口。 硬掩模层位于其中布置有互连线的电介质层上。 互连线蚀刻开口在互连线上形成对准。 将嵌段共聚物引入到互连线蚀刻开口中。 嵌段共聚物被组装以形成沿着互连线蚀刻开口的长度间隔开的多个组装结构。 组装的结构在设置在电介质层内的互连线上直接对准。
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公开(公告)号：US08959465B2
公开(公告)日：2015-02-17
申请号：US13997565
申请日：2011-12-30
CPC分类号： G06F17/5009 , G03F1/36 , G03F1/70 , G06F17/5068
摘要： Techniques are provided for determining how thick or how deep to make the phased regions of a lithography mask. One example embodiment provides a method that includes: providing a first mask layout design including a first test set, and providing a second mask layout design including a second test set, wherein the second test set is larger than the first test set; simulating critical dimensions through focus of structures of interest in the first test set for a range of phase depths/thicknesses, and selecting an initial preferred mask phase depth/thickness based on results of the simulating; and generating a fast thick-mask model (FTM) at the initial preferred phase depth/thickness, and correcting the second test set of the second mask layout design using the FTM, thereby providing an optimized mask layout design. A mask having the optimized mask layout design may be implemented to give the optimum patterning.
摘要翻译： 提供了用于确定制造光刻掩模的相位区域的厚度或深度的技术。 一个示例性实施例提供了一种方法，其包括：提供包括第一测试集的第一掩模布局设计，以及提供包括第二测试集的第二掩模布局设计，其中所述第二测试集大于所述第一测试集; 通过针对一系列相位深度/厚度的第一测试集合中关注的结构的焦点来模拟关键尺寸，并且基于模拟结果选择初始优选的掩模相位深度/厚度; 并且以最初的优选相位深度/厚度生成快速厚掩模模型（FTM），并且使用FTM校正第二掩模布局设计的第二测试集，由此提供优化的掩模布局设计。 可以实施具有优化的掩模布局设计的掩模以给出最佳图案化。
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公开(公告)号：US20140191372A1
公开(公告)日：2014-07-10
申请号：US13976077
申请日：2011-12-29
CPC分类号： H01L21/02587 , H01L21/02658 , H01L21/0337 , H01L21/28 , H01L21/76816 , H01L29/0684 , Y10S438/942
摘要： Spacer-based pitch division lithography techniques are disclosed that realize pitches with both variable line widths and variable space widths, using a single spacer deposition. The resulting feature pitches can be at or below the resolution limit of the exposure system being used, but they need not be, and may be further reduced (e.g., halved) as many times as desired with subsequent spacer formation and pattern transfer processes as described herein. Such spacer-based pitch division techniques can be used, for instance, to define narrow conductive runs, metal gates and other such small features at a pitch smaller than the original backbone pattern.
摘要翻译： 公开了使用单个间隔物沉积来实现具有可变线宽度和可变空间宽度的间距的基于间隔物的间距光刻技术。 所得到的特征间距可以处于或低于所使用的曝光系统的分辨率极限，但是它们不需要并且可以进一步减少（例如，减半），如所需的随后的间隔物形成和图案转移过程所需的多次 这里。 这种基于间隔物的螺距分割技术可以用于例如以比原始骨架图案小的间距来限定窄导电线，金属栅极和其它这样的小特征。
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公开(公告)号：US20130320456A1
公开(公告)日：2013-12-05
申请号：US13995678
申请日：2011-12-22
IPC分类号： H01L21/28 , H01L27/085
CPC分类号： H01L21/76897 , H01L21/28008 , H01L21/30625 , H01L21/32 , H01L21/76805 , H01L21/823431 , H01L21/823437 , H01L21/823468 , H01L21/823475 , H01L21/823481 , H01L23/535 , H01L27/0207 , H01L27/088 , H01L27/0886 , H01L29/0653 , H01L29/66545
摘要： Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.
摘要翻译： 描述门对齐的触点和形成栅极对准触点的方法。 例如，制造半导体结构的方法包括在形成在衬底上方的有源区上方形成多个栅极结构。 栅极结构各自包括栅极介电层，栅电极和侧壁间隔物。 形成多个接触插塞，每个接触插塞直接形成在多个门结构的两个相邻门结构的侧壁间隔件之间。 形成多个触点，每个触点直接形成在多个栅极结构的两个相邻栅极结构的侧壁间隔件之间。 在形成多个接触插塞之后形成多个触点和多个栅极结构。
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公开(公告)号：US20090267175A1
公开(公告)日：2009-10-29
申请号：US12111702
申请日：2008-04-29
IPC分类号： H01L21/308 , H01L27/00
CPC分类号： H01L21/308 , H01L21/0271 , H01L21/3086 , H01L21/3088
摘要： Double patterning techniques and structures are generally described. In one example, a method includes depositing a first photoresist to a semiconductor substrate, forming a first integrated circuit (IC) pattern in the first photoresist, the first IC pattern comprising one or more trench structures, protecting the first IC pattern in the first photoresist from actions that form a second IC pattern in a second photoresist, depositing the second photoresist to the first IC pattern, and forming the second IC pattern in the second photoresist, the second IC pattern comprising one or more structures that are sufficiently close to the one or more trench structures of the first IC pattern to cause scumming of the second photoresist in the one or more trench structures of the first IC pattern.
摘要翻译： 通常描述双重图案形成技术和结构。 在一个实例中，一种方法包括将第一光致抗蚀剂沉积到半导体衬底，在第一光致抗蚀剂中形成第一集成电路（IC）图案，第一IC图案包括一个或多个沟槽结构，保护第一光致抗蚀剂中的第一IC图案 从在第二光致抗蚀剂中形成第二IC图案的动作，将第二光致抗蚀剂沉积到第一IC图案，以及在第二光致抗蚀剂中形成第二IC图案，第二IC图案包括一个或多个足够接近该一个的结构 或更多个沟槽结构，以使第一IC图案的一个或多个沟槽结构中的第二光致抗蚀剂浮渣。
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