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    Coarse data aligner
    2.
    发明授权
    Coarse data aligner 有权
    粗数据对齐器

    公开(公告)号：US09209813B2

    公开(公告)日：2015-12-08

    申请号：US14146852

    申请日：2014-01-03

    Applicant: Oracle International Corporation

    Inventor： Robert P. Masleid

    IPC: H03L7/00 ,  H03L7/14 ,  H03L7/099 ,  H03L7/081

    CPC classification number: H03L7/00 ,  H03K5/135 ,  H03L7/0814 ,  H03L7/0991 ,  H03L2207/50 ,  H04L7/0338

    Abstract: An alignment circuit is disclosed. In one embodiment, the circuit includes a shift register having a plurality of serially-coupled storage elements each configured to receive a first signal on a respective clock input, wherein a data input of a first one of the serially-coupled storage elements is configured to receive a second signal. The circuit further includes a detector configured to detect a position of a logical transition based on data shifted into the shift register and an encoder configured to generate selection signals based on the position of the logical transition. A multiplexer tree configured to select a bit position of one of the plurality of serially-coupled storage elements based on the selection signals, wherein an output of the multiplexer tree is a third signal that is a version of the second signal.

    Abstract translation: 公开了一种对准电路。 在一个实施例中，电路包括具有多个串联耦合的存储元件的移位寄存器，每个存储元件被配置为在相应的时钟输入上接收第一信号，其中串行耦合存储元件中的第一个的数据输入被配置为 接收第二个信号。 电路还包括检测器，其被配置为基于移入到移位寄存器中的数据检测逻辑转换的位置;以及编码器，被配置为基于逻辑转换的位置产生选择信号。 多路复用器树，其被配置为基于所述选择信号来选择所述多个串行耦合存储元件中的一个的位位置，其中所述多路复用器树的输出是作为所述第二信号的版本的第三信号。

    Combo dynamic flop with scan
    3.
    发明授权
    Combo dynamic flop with scan 有权
    组合动态触发器与扫描

    公开(公告)号：US08904254B2

    公开(公告)日：2014-12-02

    申请号：US13673503

    申请日：2012-11-09

    Applicant: Oracle International Corporation

    Inventor： Robert P. Masleid ,  Ali Vahidsafa

    IPC: G01R31/28

    CPC classification number: G01R31/318541

    Abstract: A combo dynamic flop with scan flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a dynamic latch circuit and a static latch circuit. The dynamic latch circuit includes a dynamic latch storage node. The static latch circuit includes a static storage node driven by the dynamic latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit, a scan storage node, and a scan feed-forward circuit driven from the static latch. The output buffer circuit includes a dynamic latch driver driven from the dynamic latch circuit and a static driver driven from the static latch circuit.

    Abstract translation: 具有扫描电路的组合动态触发器包括触发器电路，扫描控制电路和输出缓冲电路。 触发器电路包括动态锁存电路和静态锁存电路。 动态锁存电路包括动态锁存存储节点。 静态锁存电路包括由动态锁存器驱动的静态存储节点。 扫描控制电路包括扫描从机前馈电路，扫描锁存电路和由扫描反馈电路驱动的扫描驱动电路。 扫描锁存电路包括扫描反馈电路，扫描存储节点和从静态锁存器驱动的扫描前馈电路。 输出缓冲电路包括从动态锁存电路驱动的动态锁存驱动器和从静态锁存电路驱动的静态驱动器。

    Rotational Synchronizer Circuit for Metastablity Resolution
    4.
    发明申请
    Rotational Synchronizer Circuit for Metastablity Resolution 有权
    旋转同步电路，用于可转换分辨率

    公开(公告)号：US20140210526A1

    公开(公告)日：2014-07-31

    申请号：US13755056

    申请日：2013-01-31

    Applicant: ORACLE INTERNATIONAL CORPORATION

    Inventor： Robert P. Masleid ,  Ali Vahidsafa

    IPC: H03L7/00

    CPC classification number: H03L7/00 ,  H04L7/005 ,  H04L7/02 ,  H04L25/05

    Abstract: A rotational synchronizer for metastability resolution is disclosed. A synchronizer includes a plurality of M+1 latches each coupled to receive data through a common data input. The synchronizer further includes a multiplexer having a N inputs each coupled to receive data from an output of a corresponding one of the M+1 latches, and an output, wherein the multiplexer is configured to select one of its inputs to be coupled to the output. A control circuit is configured to cause the multiplexer to sequentially select outputs of the M+1 latches responsive to N successive clock pulses, and further configured to cause the M+1 latches to sequentially latch data received through the common data input.

    Abstract translation: 公开了一种用于亚稳定性分辨率的旋转同步器。 同步器包括多个M + 1个锁存器，每个锁存器被耦合以通过公共数据输入来接收数据。 所述同步器还包括多路复用器，其具有N个输入端，每个输入端分别被耦合以从所述M + 1锁存器中对应的一个锁存器的输出端接收数据，以及输出端，其中，所述多路复用器被配置为选择其输入之一耦合到所述输出端 。 控制电路被配置为使得多路复用器响应于N个连续时钟脉冲顺序地选择M + 1个锁存器的输出，并且还被配置为使得M + 1锁存器顺序地锁存通过公共数据输入接收到的数据。

    DIGITAL ENCODING OF PARALLEL BUSSES TO SUPPRESS SIMULTANEOUS SWITCHING OUTPUT NOISE
    6.
    发明申请
    DIGITAL ENCODING OF PARALLEL BUSSES TO SUPPRESS SIMULTANEOUS SWITCHING OUTPUT NOISE 有权
    数字编码并行总线同时抑制同时开关输出噪声

    公开(公告)号：US20160164539A1

    公开(公告)日：2016-06-09

    申请号：US14563485

    申请日：2014-12-08

    Applicant: Oracle International Corporation

    Inventor： Robert P. Masleid ,  Don Draper ,  Venkat Krishnaswamy ,  Paul Loewenstein

    IPC: H03M13/21 ,  G06F11/16

    CPC classification number: G06F11/1625 ,  G06F11/00 ,  H03M5/00 ,  H03M7/00 ,  H03M13/09

    Abstract: An apparatus and method for encoding data are disclosed that may allow for different encoding levels of transmitted data. The apparatus may include an encoder unit and a plurality of transceiver units. The encoder unit may be configured to receive a plurality of data words, where each data word includes N data bits, wherein N is a positive integer greater than one, and encode a first data word of the plurality of data words. The encoded first data word may include M data bits, where M is a positive integer greater than N. Each transceiver unit may transmit a respective data bit of the encoded first data word. The encoder unit may be further configured to receive information indicative of a quality of transmission of the encoded first data word, and encode a second data word of the plurality of data words dependent upon the quality.

    Abstract translation: 公开了一种用于编码数据的装置和方法，其可以允许发送数据的不同编码级别。 该装置可以包括编码器单元和多个收发器单元。 编码器单元可以被配置为接收多个数据字，其中每个数据字包括N个数据位，其中N是大于1的正整数，并且对多个数据字的第一数据字进行编码。 编码的第一数据字可以包括M个数据位，其中M是大于N的正整数。每个收发器单元可以发送编码的第一数据字的相应数据位。 编码器单元还可以被配置为接收指示编码的第一数据字的传输质量的信息，并且根据质量来编码多个数据字中的第二数据字。

    Phase aligner with short lock time
    7.
    发明授权
    Phase aligner with short lock time 有权
    相位对准器，锁定时间短

    公开(公告)号：US09136850B2

    公开(公告)日：2015-09-15

    申请号：US14146883

    申请日：2014-01-03

    Applicant: Oracle International Corporation

    Inventor： Robert P. Masleid ,  Anand Dixit

    IPC: H03L7/00 ,  H03K5/14

    CPC classification number: H03L7/00 ,  H03K5/14

    Abstract: A phase alignment circuit is disclosed. In one embodiment, the circuit includes a register configured to capture and store, in parallel from a delay unit, a plurality of samples of a first signal, responsive to a change of state of a second signal. The circuit further includes a detection circuit configured to detect a bit position in the register at which a state change of the first signal occurs based on a concurrent evaluation of all samples of the first signal. Selection circuitry in the phase alignment circuit is configured to select an output from a one of a plurality of delay elements of the delay unit based on in the bit position at which the state change was detected. The selection circuitry is configured to output a third signal that is a delayed version of the first signal.

    Abstract translation: 公开了一种相位对准电路。 在一个实施例中，电路包括寄存器，其被配置为响应于第二信号的状态改变而从延迟单元并行存储和存储第一信号的多个样本。 该电路还包括检测电路，该检测电路被配置为基于对第一信号的所有采样的并发评估来检测在第一信号的状态变化发生的寄存器中的位位置。 相位对准电路中的选择电路被配置为基于在检测到状态改变的位位置中选择来自延迟单元的多个延迟元件中的一个的输出。 选择电路被配置为输出作为第一信号的延迟版本的第三信号。

    Phase Aligner with Short Lock Time
    8.
    发明申请
    Phase Aligner with Short Lock Time 有权
    相位调整器具有短锁定时间

    公开(公告)号：US20150194968A1

    公开(公告)日：2015-07-09

    申请号：US14146883

    申请日：2014-01-03

    Applicant: ORACLE INTERNATIONAL CORPORATION

    Inventor： Robert P. Masleid ,  Anand Dixit

    IPC: H03L7/00 ,  H03K5/14

    CPC classification number: H03L7/00 ,  H03K5/14

    Abstract: A phase alignment circuit is disclosed. In one embodiment, the circuit includes a register configured to capture and store, in parallel from a delay unit, a plurality of samples of a first signal, responsive to a change of state of a second signal. The circuit further includes a detection circuit configured to detect a bit position in the register at which a state change of the first signal occurs based on a concurrent evaluation of all samples of the first signal. Selection circuitry in the phase alignment circuit is configured to select an output from a one of a plurality of delay elements of the delay unit based on in the bit position at which the state change was detected. The selection circuitry is configured to output a third signal that is a delayed version of the first signal.

    Abstract translation: 公开了一种相位对准电路。 在一个实施例中，电路包括寄存器，其被配置为响应于第二信号的状态改变而从延迟单元并行存储和存储第一信号的多个样本。 该电路还包括检测电路，该检测电路被配置为基于对第一信号的所有采样的并发评估来检测在第一信号的状态变化发生的寄存器中的位位置。 相位对准电路中的选择电路被配置为基于在检测到状态改变的位位置中选择来自延迟单元的多个延迟元件中的一个的输出。 选择电路被配置为输出作为第一信号的延迟版本的第三信号。

    POST-SILICON REPAIR OF ON-DIE NETWORKS
    9.
    发明申请
    POST-SILICON REPAIR OF ON-DIE NETWORKS 有权
    电脑网络后硅修复

    公开(公告)号：US20140140205A1

    公开(公告)日：2014-05-22

    申请号：US13681052

    申请日：2012-11-19

    Applicant: ORACLE INTERNATIONAL CORPORATION

    Inventor： Robert P. Masleid ,  Paul J. Dickinson ,  Murali M. R. Gala ,  Karl P. Dahlgren

    IPC: H04L29/14

    CPC classification number: H04L29/14 ,  H04L49/109 ,  H04L49/557

    Abstract: A method and apparatus for post-silicon repair of on-die networks is disclosed. In one embodiment, an integrated circuit includes a first network node of an on-chip network configured to couple each of a plurality of functional units to at least one other one of the plurality of functional units. The first network node includes a plurality of ports. Each of the plurality of ports includes a plurality of multiplexers configured to substitute a spare channel of the network node into the network responsive to a test determining that another one of a plurality of channels is defective.

    Abstract translation: 公开了一种用于片上网络后硅修复的方法和装置。 在一个实施例中，集成电路包括片上网络的第一网络节点，其被配置为将多个功能单元中的每一个耦合到所述多个功能单元中的至少另一个功能单元。 第一网络节点包括多个端口。 多个端口中的每一个包括多个复用器，其被配置为响应于确定多个信道中的另一个是有缺陷的测试来将网络节点的备用信道替换到网络中。

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