公开(公告)号：US12119042B2

公开(公告)日：2024-10-15

申请号：US18222808

申请日：2023-07-17

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Frederick A. Ware

IPC: G06F1/04 ,  G06F13/42 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C7/04 ,  G11C29/02 ,  H04L7/00

CPC classification number: G11C11/4076 ,  G06F1/04 ,  G06F13/4243 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C7/04 ,  G11C7/1078 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254 ,  H04L7/0008 ,  Y02D10/00

Abstract: A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase relationship with the data signals. A data strobe signal is driven to the memory device on a second dedicated link. Phase information is received from the memory device. The phase information being generated internal to the memory device and based on a comparison between the timing signal and a version of the data strobe signal internally distributed within the memory device. A phase of the data strobe signal is adjusted relative to the timing signal based on the received phase information.

公开(公告)号：US20230359572A1

公开(公告)日：2023-11-09

申请号：US18135095

申请日：2023-04-14

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Ian P. Shaeffer ,  John Eble

IPC: G11C7/22 ,  G06F1/06 ,  G06F1/04 ,  G06F1/10 ,  G06F1/08 ,  G06F13/16

CPC classification number: G06F13/1689 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  G06F13/161 ,  G06F13/1657 ,  G11C7/222 ,  G11C7/04

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

公开(公告)号：US11750359B2

公开(公告)日：2023-09-05

申请号：US17676425

申请日：2022-02-21

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe

IPC: H04L7/033 ,  H04L7/00

CPC classification number: H04L7/0332 ,  H04L7/0008 ,  H04L7/0033 ,  H04L7/0037

Abstract: An integrated circuit receiver is disclosed comprising a data receiving circuit responsive to a timing signal to detect a data signal and an edge receiving circuit responsive to the timing signal to detect a transition of the data signal. One of the data or edge receiving circuits comprises an integrating receiver circuit while the other of the data or edge sampling circuits comprises a sampling receiver circuit.

公开(公告)号：US20220070032A1

公开(公告)日：2022-03-03

申请号：US17400945

申请日：2021-08-12

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Fariborz Assaderaghi ,  Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Qi Lin

IPC: H04L25/03 ,  H01J37/00 ,  H01L21/311 ,  H01L21/67 ,  H01L21/683 ,  H01L21/768 ,  H01L29/66

Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

公开(公告)号：US20200373169A1

公开(公告)日：2020-11-26

申请号：US16885948

申请日：2020-05-28

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Fariborz Assaderaghi ,  Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Qi Lin

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/683 ,  H01L29/66 ,  H01L21/67 ,  H01J37/00

Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

公开(公告)号：US10686632B2

公开(公告)日：2020-06-16

申请号：US16182724

申请日：2018-11-07

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Fariborz Assaderaghi ,  Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Qi Lin

IPC: H04L25/03

Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

公开(公告)号：US10541693B2

公开(公告)日：2020-01-21

申请号：US16242475

申请日：2019-01-08

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Brian S. Leibowitz ,  Hsuan-Jung Su ,  John Cronan Eble, III ,  Barry William Daly ,  Lei Luo ,  Teva J. Stone ,  John Wilson ,  Jihong Ren ,  Wayne D. Dettloff

IPC: H03L7/091 ,  H03K5/156 ,  H03L7/00 ,  G11C7/10 ,  G11C7/22 ,  H04L7/00 ,  H04L7/033 ,  H03L7/08 ,  H03L7/099 ,  G11C7/04

Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

公开(公告)号：US10536304B2

公开(公告)日：2020-01-14

申请号：US15670916

申请日：2017-08-07

Applicant: Rambus Inc.

Inventor： Qi Lin ,  Brian Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Kyung Suk Oh ,  Jared L. Zerbe

IPC: H04L25/03 ,  H04L7/00 ,  H04L7/033 ,  H04L12/26

Abstract: A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

公开(公告)号：US10418089B2

公开(公告)日：2019-09-17

申请号：US15389407

申请日：2016-12-22

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Frederick A. Ware

IPC: G06F1/04 ,  G06F13/42 ,  G11C11/4076 ,  G11C7/10 ,  G11C7/22 ,  G11C7/04 ,  G11C29/02 ,  H04L7/00

Abstract: A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase relationship with the data signals. A data strobe signal is driven to the memory device on a second dedicated link. Phase information is received from the memory device. The phase information being generated internal to the memory device and based on a comparison between the timing signal and a version of the data strobe signal internally distributed within the memory device. A phase of the data strobe signal is adjusted relative to the timing signal based on the received phase information.

公开(公告)号：US20190260364A1

公开(公告)日：2019-08-22

申请号：US16279617

申请日：2019-02-19

Applicant: Rambus Inc.

Inventor： Brian Hing-Kit Tsang ,  Jared L. Zerbe

IPC: H03K5/133 ,  H03L7/00 ,  G11C8/18 ,  G11C7/10 ,  G11C7/22 ,  G06F13/16 ,  H03K7/06 ,  H03K3/03

Abstract: Methods and apparatuses for communicating information are described. In some embodiments, a first integrated circuit (IC) provides a clock signal and a data signal to a second IC, wherein the data bits of the data signal are timed according to the clock signal, and wherein the frequency of the clock signal is capable of being changed even when the data signal is valid.