公开(公告)号：US12119331B2

公开(公告)日：2024-10-15

申请号：US17677453

申请日：2022-02-22

申请人： Samsung Electronics Co., Ltd.

发明人： Ju-Il Choi ,  Gyuho Kang ,  Heewon Kim ,  Sechul Park ,  Jongho Park ,  Junyoung Park

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L23/48 ,  H01L23/538 ,  H01L25/10 ,  H01L25/065

CPC分类号： H01L25/105 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/08 ,  H01L24/32 ,  H01L23/49833 ,  H01L24/80 ,  H01L25/0657 ,  H01L2224/08237 ,  H01L2224/32225 ,  H01L2224/80895 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1431 ,  H01L2924/1434

摘要： Disclosed is a semiconductor package comprising an interposer substrate having first and second surfaces opposite each other and including a wiring layer adjacent to the first surface, a semiconductor chip on the first surface of the interposer substrate, a passivation layer on the first surface of the interposer substrate and covering the semiconductor chip, and redistribution patterns in the passivation layer and connected to the semiconductor chip. The semiconductor chip has third and fourth surfaces opposite to each other. The third surface of the semiconductor chip faces the first surface of the interposer substrate. The redistribution patterns are connected to the fourth surface of the semiconductor chip. The semiconductor chip includes chip pads adjacent to the third surface and chip through electrodes connected to the chip pads. Each of the chip pads is directly bonded to a corresponding one of wiring patterns in the wiring layer.

公开(公告)号：US11923309B2

公开(公告)日：2024-03-05

申请号：US17210044

申请日：2021-03-23

申请人： Samsung Electronics Co., Ltd.

发明人： Hyunsu Hwang ,  Junyun Kweon ,  Jumyong Park ,  Jin Ho An ,  Dongjoon Oh ,  Chungsun Lee ,  Ju-Il Choi

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L25/065 ,  H01L25/10

CPC分类号： H01L23/5383 ,  H01L21/4857 ,  H01L23/5386 ,  H01L25/0652 ,  H01L25/105 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

摘要： Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a redistribution substrate including redistribution line patterns in a dielectric layer, and a semiconductor chip on the redistribution substrate. The semiconductor chip includes chip pads electrically connected to the redistribution line patterns. Each of the redistribution line patterns has a substantially planar top surface and a nonplanar bottom surface. Each of the redistribution line patterns includes a central portion and edge portions on opposite sides of the central portion. Each of the redistribution line patterns has a first thickness as a minimum thickness at the central portion and a second thickness as a maximum thickness at the edge portions.

公开(公告)号：US11444014B2

公开(公告)日：2022-09-13

申请号：US16830361

申请日：2020-03-26

申请人： Samsung Electronics Co., Ltd.

发明人： Jinho Chun ,  Jin Ho An ,  Teahwa Jeong ,  Jeonggi Jin ,  Ju-Il Choi ,  Atsushi Fujisaki

IPC分类号： H01L23/49 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31

摘要： There are provided semiconductor packages including a redistribution substrate and a semiconductor chip mounted on the redistribution substrate. The redistribution substrate may include a lower protective layer, a first conductive pattern disposed on the lower protective layer, a first insulating layer surrounding the first conductive pattern and disposed on the lower protective layer, and a second insulating layer disposed on the first insulating layer. The first insulating layer may include a first upper surface that includes a first flat portion extending parallel to an upper surface of the lower protective layer, and a first recess facing the lower protective layer and in contact with the first conductive pattern. The first recess may be directly connected to the first conductive pattern.

公开(公告)号：US20180218966A1

公开(公告)日：2018-08-02

申请号：US15936019

申请日：2018-03-26

申请人： Samsung Electronics Co., Ltd.

发明人： Ju-Il Choi ,  KWANG-JIN MOON ,  BYUNG-LYUL PARK ,  JIN-HO AN ,  ATSUSHI FUJISAKI

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L25/18 ,  H01L25/065 ,  H01L23/532

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/03618 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/05155 ,  H01L2224/05546 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05564 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/13023 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16013 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/01047

摘要： A semiconductor device can include a substrate that has a surface. A via structure can extend through the substrate toward the surface of the substrate, where the via structure includes an upper surface. A pad structure can be on the surface of the substrate, where the pad structure can include a lower surface having at least one protrusion that is configured to protrude toward the upper surface of the via structure.

公开(公告)号：US12014972B2

公开(公告)日：2024-06-18

申请号：US17403154

申请日：2021-08-16

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Ju-Il Choi ,  Kwang-Jin Moon ,  Byung-Lyul Park ,  Jin-Ho An ,  Atsushi Fujisaki

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L24/14 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/03618 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/05155 ,  H01L2224/05546 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05564 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/10 ,  H01L2224/13023 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16013 ,  H01L2224/16111 ,  H01L2224/16112 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2924/00 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05684 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05611 ,  H01L2924/013 ,  H01L2924/01047 ,  H01L2224/03618 ,  H01L2924/00014 ,  H01L2224/13139 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/00014

摘要： A method of manufacturing a semiconductor device is provided. The method includes forming a preliminary via structure through a portion of a substrate; partially removing the substrate to expose a portion of the preliminary via structure; forming a protection layer structure on the substrate to cover the portion of the preliminary via structure that is exposed; partially etching the protection layer structure to form a protection layer pattern structure and to partially expose the preliminary via structure; wet etching the preliminary via structure to form a via structure; and forming a pad structure on the via structure to have a flat top surface.

公开(公告)号：US11742271B2

公开(公告)日：2023-08-29

申请号：US17306988

申请日：2021-05-04

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Gyuho Kang ,  Seong-Hoon Bae ,  Jin Ho An ,  Teahwa Jeong ,  Ju-Il Choi ,  Atsushi Fujisaki

IPC分类号： H01L23/498 ,  H01L25/10 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L23/49822 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/05015 ,  H01L2224/05017 ,  H01L2224/05555 ,  H01L2224/05558 ,  H01L2224/05582 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/182

摘要： A semiconductor package includes; a redistribution substrate including a redistribution pattern, a semiconductor chip mounted on a top surface of the redistribution substrate, and a connection terminal between the semiconductor chip and the redistribution substrate. The redistribution substrate further includes; a pad structure including a pad interconnection and a pad via, disposed between the redistribution pattern and the connection terminal, wherein the pad structure is electrically connected to the redistribution pattern and a top surface of the pad structure contacts the connection terminal, a shaped insulating pattern disposed on a top surface of the redistribution pattern, and a pad seed pattern disposed on the redistribution pattern and covering the shaped insulating pattern.

公开(公告)号：US11694978B2

公开(公告)日：2023-07-04

申请号：US17697830

申请日：2022-03-17

申请人： Samsung Electronics Co., Ltd.

发明人： Ju-Il Choi ,  Un-Byoung Kang ,  Jin Ho An ,  Jongho Lee ,  Jeonggi Jin ,  Atsushi Fujisaki

IPC分类号： H01L23/00

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0346 ,  H01L2224/03614 ,  H01L2224/0401 ,  H01L2224/0508 ,  H01L2224/05016 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/11849 ,  H01L2224/13026 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155

摘要： Semiconductor devices are provided. A semiconductor device includes an insulating layer and a conductive element in the insulating layer. The semiconductor device includes a first barrier pattern in contact with a surface of the conductive element and a surface of the insulating layer. The semiconductor device includes a second barrier pattern on the first barrier pattern. Moreover, the semiconductor device includes a metal pattern on the second barrier pattern. Related semiconductor packages are also provided.

公开(公告)号：US11676887B2

公开(公告)日：2023-06-13

申请号：US17318227

申请日：2021-05-12

申请人： Samsung Electronics Co., Ltd.

发明人： Jeonggi Jin ,  Gyuho Kang ,  Solji Song ,  Un-Byoung Kang ,  Ju-Il Choi

IPC分类号： H01L23/48 ,  H01L23/498 ,  H01L23/00

CPC分类号： H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227

摘要： A semiconductor package may include a redistribution substrate having a first surface and a second surface, opposite to each other, a semiconductor chip on the first surface of the redistribution substrate, and a solder pattern on the second surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern coupled to the solder pattern, a first redistribution pattern on the under-bump pattern, the first redistribution pattern including a first via portion and a first wire portion, and a first seed pattern between the under-bump pattern and the first redistribution pattern and on a side surface of the first via portion and a bottom surface of the first wire portion. A bottom surface of the first seed pattern may be at a level lower than a top surface of the under-bump pattern.

公开(公告)号：US11637058B2

公开(公告)日：2023-04-25

申请号：US17099929

申请日：2020-11-17

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Ju-Il Choi ,  Jumyong Park ,  Jin Ho An ,  Chungsun Lee ,  Teahwa Jeong ,  Jeonggi Jin

IPC分类号： H01L23/48 ,  H01L23/498 ,  H01L25/10 ,  H01L23/31 ,  H01L25/065

摘要： An interconnection structure includes a dielectric layer, and a wiring pattern in the dielectric layer. The wiring pattern includes a via body, a first pad body that vertically overlaps the via body, and a line body that extends from the first pad body. The via body, the first pad body, and the line body are integrally connected to each other, and a level of a bottom surface of the first pad body is lower than a level of a bottom surface of the line body.

公开(公告)号：US11488860B2

公开(公告)日：2022-11-01

申请号：US16938259

申请日：2020-07-24

申请人： Samsung Electronics Co., Ltd.

发明人： Su-jeong Park ,  Dong-chan Lim ,  Kwang-jin Moon ,  Ju-bin Seo ,  Ju-Il Choi ,  Atsushi Fujisaki

IPC分类号： H01L23/48 ,  H01L21/768

摘要： An integrated circuit device includes a substrate, a landing pad on the substrate, and a through-via structure passing through the substrate and connected to the landing pad. The through-via structure may include a conductive plug, a first conductive barrier layer covering a sidewall and a lower surface of the conductive plug, and a second conductive barrier layer covering a sidewall of the first conductive barrier layer.