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    METHOD OF FORMING METAL INTERCONNECTIONS OF SEMICONDUCTOR DEVICE
    2.
    发明申请
    METHOD OF FORMING METAL INTERCONNECTIONS OF SEMICONDUCTOR DEVICE 有权
    形成金属互连的半导体器件的方法

    公开(公告)号：US20140339701A1

    公开(公告)日：2014-11-20

    申请号：US14448115

    申请日：2014-07-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： WooJin JANG ,  Kyoungwoo LEE

    IPC: H01L23/522 ,  H01L23/532

    CPC classification number: H01L23/53238 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L2224/13

    Abstract: A method of forming a metal interconnection of semiconductor device is provided. The method includes forming a low-k dielectric layer including an opening; forming a barrier metal pattern conformally covering a bottom surface and an inner sidewall of the opening; forming a metal pattern exposing a part of the inner sidewall of the barrier metal pattern in the opening; forming a metal capping layer on the top surfaces of the metal pattern and the low-k dielectric layer using a selective chemical vapor deposition process, wherein the thickness of the metal capping layer on the metal pattern is greater than the thickness of the metal capping layer on the low-k dielectric layer; and forming a metal capping pattern covering the top surface of the metal pattern by planarizing the metal capping layer down to the top surface of the low-k dielectric layer.

    Abstract translation: 提供一种形成半导体器件的金属互连的方法。 该方法包括形成包括开口的低k电介质层; 形成保形地覆盖所述开口的底部表面和内侧壁的阻挡金属图案; 形成露出所述开口中的所述阻挡金属图案的内侧壁的一部分的金属图案; 使用选择性化学气相沉积工艺在金属图案和低k电介质层的顶表面上形成金属覆盖层，其中金属图案上的金属覆盖层的厚度大于金属覆盖层的厚度 在低k电介质层上; 以及通过将金属覆盖层平坦化到低k电介质层的顶表面来形成覆盖金属图案的顶表面的金属覆盖图案。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230005838A1

    公开(公告)日：2023-01-05

    申请号：US17672990

    申请日：2022-02-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaemyung CHOI ,  Kyoungwoo LEE ,  Nayon KIM ,  Seonghun LIM ,  Sungyup JUNG

    IPC: H01L23/522 ,  H01L21/033 ,  H01L21/768 ,  H01L23/528

    Abstract: A semiconductor device includes a lower structure, a first interlayer dielectric (ILD) on the lower structure, first pattern regions extending inside the first ILD in a first direction, the first pattern regions being spaced apart from each other in a second direction perpendicular to the first direction, each of the first pattern regions including at least one first pattern, and both ends of the at least one first pattern in the first direction being concave, and second pattern regions extending inside the first ILD in the first direction, the second pattern regions being spaced apart from each other in the second direction and alternating with the first pattern regions in the second direction, and each of the second pattern regions including at least one second pattern.

    METHOD OF FABRICATING SEMICONDUCTOR DEVICE
    4.
    发明申请
    METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220319907A1

    公开(公告)日：2022-10-06

    申请号：US17537571

    申请日：2021-11-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyoungwoo LEE ,  Minkwon CHOI

    IPC: H01L21/762 ,  H01L29/66 ,  H01L21/311 ,  H01L21/308

    Abstract: Disclosed is a semiconductor device fabrication method including forming an interlayer dielectric layer and a lower mask layer on a substrate, forming on the lower mask layer first and second upper mask patterns spaced apart from each other in a first direction, wherein each of the first and second upper mask patterns has a line part extending in a second direction and a first protruding part protruding from the line part, forming a spacer covering sidewalls of the line parts of the first and second upper mask patterns and a filling pattern filling a space between the first protruding parts of the first and second upper mask patterns, etching the lower mask layer to form lower mask patterns, etching the interlayer dielectric layer to form grooves on the interlayer dielectric layer, and forming wiring lines in the grooves.

    SEMICONDUCTOR DEVICE
    6.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250098264A1

    公开(公告)日：2025-03-20

    申请号：US18604031

    申请日：2024-03-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sangcheol NA ,  Beomjin KIM ,  Yoolim AHN ,  Kyoungwoo LEE ,  Minseung LEE ,  Hyeryeong LEE ,  Keun Hwi CHO ,  Seungseok HA

    IPC: H01L29/417 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

    Abstract: A semiconductor device includes an insulating layer including a first surface, a second surface, and an element isolation trench, an insulating pattern on the first surface of the insulating layer, an active pattern on the insulating pattern and including channel patterns, a source/drain pattern on at least one side of the active pattern, a lower wiring structure on the second surface of the insulating layer, and a through-via that extending in the insulating layer and connecting the source/drain pattern and the lower wiring structure, where the insulating pattern may include a first portion between the insulating layer and the active pattern, a second portion surrounding at least a portion of the through-via, and a third portion on a bottom surface of the element isolation trench.

    SEMICONDUCTOR DEVICE INCLUDING CONDUCTIVE LINE AND METHOD FOR MANUFACTURING THE SAME
    9.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING CONDUCTIVE LINE AND METHOD FOR MANUFACTURING THE SAME 有权

    公开(公告)号：US20220270890A1

    公开(公告)日：2022-08-25

    申请号：US17395030

    申请日：2021-08-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaemyung CHOI ,  Kyoungwoo LEE

    IPC: H01L21/3213 ,  H01L21/027

    Abstract: A method for manufacturing a semiconductor device including forming an insulating structure, forming a hard mask layer on the insulating structure, performing a first etching process to form a first opening at the hard mask layer, forming a first sacrificial pattern in the first opening, forming, on the hard mask layer, a first photoresist pattern including a second opening and a third opening, the second opening exposing a top surface of the first sacrificial pattern, the third opening exposing a top surface of the hard mask layer, and performing a second etching process using the first photoresist pattern as an etch mask may be provided.

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