公开(公告)号：US20240178294A1

公开(公告)日：2024-05-30

申请号：US18347929

申请日：2023-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunkyu LEE ,  Keunwook SHIN ,  Minsu SEOL

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/18 ,  H01L29/417 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/18 ,  H01L29/41733 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device may include a first electrode and a second electrode on a substrate and arranged perpendicular to a surface of the substrate, a plurality of channel layers between the first electrode and the second electrode, and a gate electrode surrounding the plurality of channel layers. The plurality of channel layers may be inclined with respect to a direction from the first electrode to the second electrode. An electronic device may include the semiconductor device.

公开(公告)号：US20230238329A1

公开(公告)日：2023-07-27

申请号：US18158233

申请日：2023-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Sangwon KIM ,  Kyung-Eun BYUN ,  Joungeun YOO ,  Eunkyu LEE ,  Changseok LEE ,  Alum JUNG

IPC: H01L23/532 ,  H01L23/528

CPC classification number: H01L23/53276 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242

Abstract: An interconnect structure may include a dielectric layer including a trench, a conductive wiring including graphene filling an inside of the trench, and a liner layer in contact with at least one surface of the conductive wiring and including a metal.

公开(公告)号：US20230072229A1

公开(公告)日：2023-03-09

申请号：US17668004

申请日：2022-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changseok LEE ,  Sangwon KIM ,  Changhyun KIM ,  Kyung-Eun BYUN ,  Eunkyu LEE

IPC: H01L27/108 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24 ,  H01L29/76 ,  H01L29/786

Abstract: Provided are a vertical-channel cell array transistor structure and a dynamic random-access memory (DRAM) device including the same. The vertical-channel cell array transistor structure includes a semiconductor substrate, a plurality of channels arranged in an array on the semiconductor substrate and each extending perpendicularly from the semiconductor substrate, a gate insulating layer on the plurality of channels, a plurality of word lines on the semiconductor substrate and extending in a first direction, and a two-dimensional (2D) material layer on at least one surface of each of the plurality of word lines.

公开(公告)号：US20220238721A1

公开(公告)日：2022-07-28

申请号：US17505955

申请日：2021-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Van Luan NGUYEN ,  Minsu SEOL ,  Eunkyu LEE ,  Junyoung KWON ,  Hyeonjin SHIN ,  Minseok YOO

IPC: H01L29/786

Abstract: A semiconductor device according to an embodiment may include a substrate, an adhesive layer, and a semiconductor layer. The semiconductor layer includes a 2D material having a layered structure. The adhesive layer is interposed between the substrate and the semiconductor layer, and has adhesiveness to a 2D material.

公开(公告)号：US20240222524A1

公开(公告)日：2024-07-04

申请号：US18507905

申请日：2023-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu SEOL ,  Eunkyu LEE ,  Junyoung KWON ,  Kyung-Eun BYUN

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/78696 ,  H01L29/0603 ,  H01L29/66795 ,  H01L29/785

Abstract: Provided are a field effect transistor, a method of manufacturing the field effect transistor, and an electronic device and an electronic apparatus each including the field effect transistor. The field effect transistor includes a channel layer disposed on a substrate, a high-k gate insulating layer disposed on the channel layer, a first composite electrode layer connected to a first side of the channel layer, a second composite electrode layer connected to a second side of the channel layer, and a gate electrode layer disposed on the gate insulating layer. At least one of the first and second composite electrode layers includes a contact resistance reducing layer in contact with the channel layer and a conductive layer in contact with the contact resistance reducing layer. The conductive layer is spaced apart from the channel layer.

公开(公告)号：US20240178307A1

公开(公告)日：2024-05-30

申请号：US18518729

申请日：2023-11-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu SEOL ,  Sungil PARK ,  Jaehyun PARK ,  Kyung-Eun BYUN ,  Eunkyu LEE ,  Junyoung KWON ,  Minseok YOO

IPC: H01L29/76 ,  H01L29/24 ,  H01L29/78

CPC classification number: H01L29/7606 ,  H01L29/24 ,  H01L29/78391

Abstract: A semiconductor device may include a multi-layer gate dielectric layer and an electronic apparatus including the semiconductor device. The semiconductor device may include a channel layer including a two-dimensional semiconductor material, a gate dielectric layer on a first area of the channel layer, a gate electrode on the gate dielectric layer, and source and drain electrodes in a second area of the channel layer. The gate dielectric layer may include a high-k dielectric layer and an intermediate dielectric layer. The intermediate dielectric layer may be between the high-k dielectric layer and the channel layer. A dielectric constant of the intermediate dielectric layer may be less than a dielectric constant of the high-k dielectric layer.

公开(公告)号：US20220328671A1

公开(公告)日：2022-10-13

申请号：US17539768

申请日：2021-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhyun KIM ,  Hyeonjin SHIN ,  Minhyun LEE ,  Taejin CHOI ,  Sangwon KIM ,  Bongseob YANG ,  Eunkyu LEE

IPC: H01L29/76 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24

Abstract: A field effect transistor structure is disclosed. The field effect transistor structure includes: a fin-shaped channel protruding from a substrate and extending in one direction; a source electrode on one side of the fin-shaped channel; a drain electrode separated from the source electrode with the fin-shaped channel therebetween; a gate insulating film surrounding side and upper surfaces of the fin-shaped channel; a gate electrode on the gate insulating film; and a two-dimensional semiconductor material layer between the gate insulating film and the gate electrode.

公开(公告)号：US20210276873A1

公开(公告)日：2021-09-09

申请号：US17190852

申请日：2021-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwon KIM ,  Kyung-Eun BYUN ,  Hyeonjin SHIN ,  Eunkyu LEE ,  Changseok LEE

IPC: C01B32/186

Abstract: A graphene manufacturing apparatus includes a reaction chamber a substrate supporter configured to structurally support a substrate inside the reaction chamber; a plasma generator configured to generate a plasma inside the reaction chamber; a first gas supply configured to supply an inert gas into the reaction chamber at a first height from an upper surface of the substrate supporter in a height direction of the reaction chamber; a second gas supply configured to supply a carbon source into the reaction chamber at a second height from the upper surface of the substrate supporter in the height direction of the reaction chamber; and a third gas supply configured to supply a reducing gas into the reaction chamber, wherein the first to third gas supply units are disposed at different heights at a third height from the upper surface of the substrate supporter in the height direction of the reaction chamber.

公开(公告)号：US20200152808A1

公开(公告)日：2020-05-14

申请号：US16740900

申请日：2020-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiyoung LEE ,  Jinseong HEO ,  Jaeho LEE ,  Haeryong KIM ,  Seongjun PARK ,  Hyeonjin SHIN ,  Eunkyu LEE ,  Sanghyun JO

IPC: H01L31/0216 ,  H01L31/028 ,  H01L31/0352 ,  H01L31/0224 ,  H01L31/18 ,  G01N21/59

Abstract: A broadband multi-purpose optical device includes a semiconductor layer having a light absorption characteristic, a first active layer having a light absorption band different from a light absorption band of the semiconductor layer, a first two-dimensional (2D) material layer adjacent to the first active layer, and a first interfacial layer configured to control a pinning potential of the semiconductor layer and the first active layer. The broadband multi-purpose optical device may further include at least one second active layer, and may include a tandem structure that further includes at least one second 2D material layer. The first active layer and the second active layer may have different light absorption bands. The broadband multi-purpose optical device may further include a second interfacial layer adjacent to the first 2D material layer.

公开(公告)号：US20170243913A1

公开(公告)日：2017-08-24

申请号：US15244073

申请日：2016-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeho LEE ,  Kiyoung LEE ,  Sangyeob LEE ,  Eunkyu LEE ,  Jinseong HEO ,  Seongjun PARK

IPC: H01L27/146 ,  H01L31/0352 ,  H01L31/109 ,  H01L31/032

CPC classification number: H01L27/14649 ,  H01L27/14621 ,  H01L27/14645 ,  H01L27/14647 ,  H01L27/14689 ,  H01L31/032 ,  H01L31/035227 ,  H01L31/109

Abstract: An image sensor may include visible light detectors and a near-infrared light detector. The near-infrared light detector may contain a material highly sensitive to near-infrared rays, and thus the size of the near-infrared light detector may be reduced.