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公开(公告)号：US20210013263A1
公开(公告)日：2021-01-14
申请号：US17030425
申请日：2020-09-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ji-Hyun JEONG , Gwan-hyeob KOH , Dae-hwan KANG
IPC: H01L27/24 , H01L27/102 , H01L45/00 , G11C13/00
Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer. The first memory cell has a side surface slope so as to have a width gradually decreasing toward its upper portion.
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公开(公告)号：US20190189692A1
公开(公告)日：2019-06-20
申请号：US16281486
申请日：2019-02-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ji-hyun JEONG , Gwan-hyeob KOH , Dae-hwan KANG
IPC: H01L27/24 , G11C13/00 , H01L45/00 , H01L27/102
CPC classification number: H01L27/2481 , G11C13/0004 , G11C13/0023 , G11C13/004 , G11C13/0069 , G11C2213/15 , G11C2213/52 , G11C2213/71 , G11C2213/72 , G11C2213/76 , G11C2213/79 , H01L27/1026 , H01L27/2427 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1293 , H01L45/144 , H01L45/16 , H01L45/1675
Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer. The first memory cell has a side surface slope so as to have a width gradually decreasing toward its upper portion.
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公开(公告)号：US20170243923A1
公开(公告)日：2017-08-24
申请号：US15288233
申请日：2016-10-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ji-hyun JEONG , Gwan-hyeob KOH , Dae-hwan KANG
CPC classification number: H01L27/2481 , G11C13/0004 , G11C13/0023 , G11C13/004 , G11C13/0069 , G11C2213/71 , G11C2213/72 , H01L27/1026 , H01L27/2427 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1293 , H01L45/144 , H01L45/16 , H01L45/1675
Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer. The first memory cell has a side surface slope so as to have a width gradually decreasing toward its upper portion.
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公开(公告)号：US20170243918A1
公开(公告)日：2017-08-24
申请号：US15257609
申请日：2016-09-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Masayuki TERAI , Gwan-hyeob KOH , Dae-hwan KANG
CPC classification number: H01L27/2427 , G11C11/1659 , G11C13/0002 , G11C13/003 , G11C2213/17 , G11C2213/71 , G11C2213/76 , G11C2213/79 , H01L27/0688 , H01L27/101 , H01L27/11582 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L43/08 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/126 , H01L45/144 , H01L45/1675
Abstract: A memory device may include a substrate, a first conductive line on the substrate and extending in a first direction, a second conductive line over the first conductive line and extending in a second direction crossing the first direction, a third conductive line over the second conductive line and extending in the first direction, a first memory cell at an intersection of the first conductive line and the second conductive line and including a first selection element layer and a first variable resistance layer, and a second memory cell at an intersection of the second conductive line and the third conductive line and including a second selection element layer and a second variable resistance layer. A first height of the first selection element layer in a third direction perpendicular to the first and second directions is different than a second height of the second selection element layer in the third direction.
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5.发明申请公开(公告)号：US20200097361A1
公开(公告)日：2020-03-26
申请号：US16575615
申请日：2019-09-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ki-seok SUH , Gwan-hyeob KOH , Yoon-jong SONG
Abstract: A memory system includes a memory cell array including a first memory area and a second memory area, an input/output circuit including input/output lines for transmitting or receiving data bits and parity bits to or from the first and second memory areas, and an error correction circuit including a plurality of sub error correction circuits including a first sub error correction circuit for performing a first error correction operation on first data bits of the first memory area received through the input/output lines, and a second sub error correction circuit for performing a second error correction operation on second data bits of the second memory area received through the input/output lines. The first memory area has a higher bit error rate than the second memory area.
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Patent Agency Ranking
公开(公告)号：US20190362791A1
公开(公告)日：2019-11-28
申请号：US16533143
申请日：2019-08-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sung-woo KIM , Jae-kyu LEE , Ki-seok SUH , Hyeong-sun HONG , Yoo-sang HWANG , Gwan-hyeob KOH
IPC: G11C14/00 , H01L27/22 , H01L27/108 , H01L27/24 , H01L45/00 , H01L43/12 , H01L43/02 , H01L43/08 , H01L29/423 , H01L23/528 , H01L29/08 , H01L27/105 , H01L27/02 , G11C11/00 , G11C7/10
Abstract: An integrated circuit (IC) device may include a single substrate that includes a single chip, and a plurality of memory cells spaced apart from one another on the substrate and having different structures. Manufacturing the IC device may include forming a plurality of first word lines in a first region of the substrate, and forming a plurality of second word lines in or on a second region of the substrate. Capacitors may be formed on the first word lines. Source lines may be formed on the second word lines. An insulation layer that covers the plurality of capacitors and the plurality of source lines may be formed in the first region and the second region. A variable resistance structure may be formed at a location spaced apart from an upper surface of the substrate by a first vertical distance, in the second region.
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公开(公告)号：US20170244030A1
公开(公告)日：2017-08-24
申请号：US15362906
申请日：2016-11-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Il-mok PARK , Gwan-hyeob KOH , Dae-hwan KANG
CPC classification number: H01L45/1233 , H01L27/2427 , H01L27/2481 , H01L45/06 , H01L45/1253 , H01L45/126 , H01L45/141 , H01L45/144 , H01L45/1675 , H01L45/1683
Abstract: A memory device including first conductive lines spaced apart from each other and extending in a first direction; second conductive lines spaced apart from each other and extending in a second direction that is different from the first direction; first memory cells having a structure that includes a selection device layer, a middle electrode layer, a variable resistance layer, and a top electrode layer; and insulating structures arranged alternately with the first memory cells in the second direction under the second conductive lines, wherein the first insulating structures have a top surface that is higher than a top surface of the first top electrode layer, and the second conductive lines have a structure that includes convex and concave portions, the convex portions being connected to the top surface of the top electrode layer and the concave portions accommodating the insulating structures between the convex portions.
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公开(公告)号：US20170069827A1
公开(公告)日：2017-03-09
申请号：US15131564
申请日：2016-04-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yong-Kyu LEE , Gwan-hyeob KOH , Hong-kook MIN
CPC classification number: H01L27/228 , H01L27/20 , H01L27/222 , H01L43/08 , H01L43/10
Abstract: A semiconductor apparatus includes a substrate, a first insulating layer on a logic region and a memory region of the substrate, a second insulating layer on the first insulating layer, a base insulating layer between the first insulating layer and second insulating layer over the logic region and the memory region, first interconnection structures passing the first insulating layer, second interconnection structures passing through the second insulating layer, a base interconnection structure passing through the base insulating layer over the logic region, and a variable resistance structure in the base insulating layer over the memory region. The variable resistance structure includes a lower electrode, a magnetoresistive device, and an upper electrode, which are sequentially stacked. The lower electrode and the upper electrode are electrically connected to one of the first interconnection structures and one of the second interconnection structures, respectively, over the memory region.
Abstract translation: 一种半导体装置，包括基板，逻辑区域上的第一绝缘层和基板的存储区域，第一绝缘层上的第二绝缘层，位于逻辑区域之间的第一绝缘层和第二绝缘层之间的基极绝缘层 存储区域，通过第一绝缘层的第一互连结构，穿过第二绝缘层的第二互连结构，在逻辑区域上穿过基极绝缘层的基底互连结构，以及基极绝缘层中的可变电阻结构， 存储区域。 可变电阻结构包括依次堆叠的下电极，磁阻器件和上电极。 下电极和上电极分别在存储区域上电连接到第一互连结构中的一个和第二互连结构中的一个。
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公开(公告)号：US20200227481A1
公开(公告)日：2020-07-16
申请号：US16835667
申请日：2020-03-31
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ji-hyun JEONG , Gwan-hyeob KOH , Dae-hwan KANG
IPC: H01L27/24 , H01L27/102 , H01L45/00 , G11C13/00
Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer. The first memory cell has a side surface slope so as to have a width gradually decreasing toward its upper portion.
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公开(公告)号：US20190013466A1
公开(公告)日：2019-01-10
申请号：US16109914
申请日：2018-08-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Il-mok PARK , Gwan-hyeob KOH , Dae-hwan KANG
CPC classification number: H01L45/1233 , H01L27/2427 , H01L27/2481 , H01L45/06 , H01L45/1253 , H01L45/126 , H01L45/141 , H01L45/144 , H01L45/1675 , H01L45/1683
Abstract: A memory device including first conductive lines spaced apart from each other and extending in a first direction; second conductive lines spaced apart from each other and extending in a second direction that is different from the first direction; first memory cells having a structure that includes a selection device layer, a middle electrode layer, a variable resistance layer, and a top electrode layer; and insulating structures arranged alternately with the first memory cells in the second direction under the second conductive lines, wherein the first insulating structures have a top surface that is higher than a top surface of the first top electrode layer, and the second conductive lines have a structure that includes convex and concave portions, the convex portions being connected to the top surface of the top electrode layer and the concave portions accommodating the insulating structures between the convex portions.
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