公开(公告)号：US08759221B2

公开(公告)日：2014-06-24

申请号：US13924817

申请日：2013-06-24

Applicant: Samsung Electronics Co., Ltd

Inventor： Jin-Woo Park ,  Hwan-Sik Lim ,  Eunchul Ahn

IPC: H01L21/302

CPC classification number: H01L21/50 ,  H01L21/563 ,  H01L23/48 ,  H01L23/58 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83385 ,  H01L2924/00012

Abstract: A package substrate, a semiconductor package having the same, and a method for fabricating the semiconductor package. The semiconductor package includes a semiconductor chip, a package substrate, and a molding layer. The package substrate provides a region mounted with the semiconductor chip. The molding layer is configured to mold the semiconductor chip. The package substrate includes a first opening portion that provides an open region connected electrically to the semiconductor chip and extends beyond sides of the semiconductor chip to be electrically connected to the semiconductor chip.

Abstract translation: 封装基板，具有该封装基板的半导体封装以及半导体封装的制造方法。 半导体封装包括半导体芯片，封装基板和模制层。 封装衬底提供安装有半导体芯片的区域。 模制层被配置成模制半导体芯片。 封装基板包括第一开口部分，该第一开口部分提供与半导体芯片电连接的开放区域，并且延伸超过半导体芯片的两侧以与半导体芯片电连接。

公开(公告)号：US08823172B2

公开(公告)日：2014-09-02

申请号：US14175162

申请日：2014-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwan-Sik Lim ,  Sunwon Kang ,  Jongho Lee

IPC: H01L23/48

CPC classification number: H01L24/14 ,  H01L23/3128 ,  H01L23/3192 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/05578 ,  H01L2224/0603 ,  H01L2224/06515 ,  H01L2224/13025 ,  H01L2224/13028 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/1411 ,  H01L2224/14515 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17517 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a semiconductor chip having a first bump group and a second bump group, and a package substrate having a first pattern for data communication with the semiconductor chip and a second pattern for supplying power to the semiconductor chip or grounding the semiconductor chip, wherein the first bump group is disposed on the first pattern and the second bump group is disposed on the second pattern.

Abstract translation: 半导体封装包括具有第一凸块组和第二凸块组的半导体芯片，以及具有用于与半导体芯片进行数据通信的第一图案的封装基板和用于向半导体芯片供电或将半导体芯片接地的第二图案， 其中所述第一凸块组设置在所述第一图案上，并且所述第二凸块组设置在所述第二图案上。

公开(公告)号：US08928150B2

公开(公告)日：2015-01-06

申请号：US13889338

申请日：2013-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moon-Gi Cho ,  Sun-Hee Park ,  Hwan-Sik Lim ,  Yong-Hwan Kwon

IPC: H01L23/48 ,  H01L23/522 ,  H01L21/768 ,  H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/5226 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76879 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/24 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68381 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/11462 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/16225 ,  H01L2224/19 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24147 ,  H01L2224/32145 ,  H01L2224/73209 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/821 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/82 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A multi-chip package may include first and second semiconductor chips, an insulating layer structure and a plug structure. The first semiconductor chip may include a first bonding pad. The second semiconductor chip may be positioned over the first semiconductor chip. The second semiconductor chip may include a second bonding pad. The insulating layer structure may cover side surfaces and at least portions of upper surfaces of the semiconductor chips. The plug structure may be formed in the insulating layer structure by a plating process. The plug structure may be arranged spaced apart from side surfaces of the semiconductor chips to electrically connect the first bonding pad and the second bonding pad with each other. A third semiconductor chip having a third bonding pad may be positioned over the second semiconductor chip. Thus, a process for forming a micro bump between the plugs need not be performed.

Abstract translation: 多芯片封装可以包括第一和第二半导体芯片，绝缘层结构和插头结构。 第一半导体芯片可以包括第一接合焊盘。 第二半导体芯片可以位于第一半导体芯片上。 第二半导体芯片可以包括第二接合焊盘。 绝缘层结构可以覆盖半导体芯片的侧表面和上表面的至少一部分。 插塞结构可以通过电镀工艺形成在绝缘层结构中。 插头结构可以布置成与半导体芯片的侧表面间隔开，以将第一焊盘和第二焊盘彼此电连接。 具有第三接合焊盘的第三半导体芯片可以位于第二半导体芯片上。 因此，不需要在插头之间形成微凸块的工序。