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公开(公告)号:US12008970B2
公开(公告)日:2024-06-11
申请号:US17727303
申请日:2022-04-22
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hyunjoon Choo , Hyunsoo Jeong , Jonghwa Choi , Jongjin Ko , Kwangyoun Kim , Jangwoo Lee , Kyungah Chang
CPC classification number: G09G3/36 , G06F3/017 , G06F3/14 , G06V20/64 , G06V40/168 , G06V40/172 , H04N7/188 , H04N23/56 , H05B47/125
Abstract: A display device is provided. The display device includes a mirror display, a three-dimensional camera positioned toward a front direction of the mirror display, and a controller configured to detect facial contours of a user from three-dimensional face images of the user photographed at at least two different time points by the three-dimensional camera, identify a change of the facial contours between the two time points based on the detected facial contours, and control the mirror display to display information about the change of the facial contours.
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公开(公告)号:USD973081S1
公开(公告)日:2022-12-20
申请号:US29778630
申请日:2021-04-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Designer: Jangwoo Lee , Yongho Kim , Seoeun Park
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公开(公告)号:US10998888B2
公开(公告)日:2021-05-04
申请号:US16861903
申请日:2020-04-29
Applicant: Samsung Electronics Co., Ltd.
Inventor: Dongho Shin , Kyungtae Kang , Junha Lee , Tongsung Kim , Jangwoo Lee , Jeongdon Ihm , Byunghoon Jeong
Abstract: A parameter monitoring circuit includes a code generation circuit configured to generate a first code, to which a first offset is applied, and a second code, to which a second offset is applied; a parameter adjustment circuit configured to generate a first parameter and a second parameter by respectively applying the first code and the second code to a current parameter; a comparator circuit configured to generate a first comparison result and a second comparison result, the first comparison result indicating a comparison result between the first parameter and a reference parameter value, and the second comparison result indicating a comparison result between the second parameter and the reference parameter value; and a parameter error detection circuit configured to detect an error in the current parameter, based on the first comparison result and the second comparison result.
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公开(公告)号:US10950521B2
公开(公告)日:2021-03-16
申请号:US16566380
申请日:2019-09-10
Applicant: Samsung Electronics Co., Ltd.
Inventor: Min-Ok Na , Jongkook Kim , Hyo-Chang Ryu , Jin-woo Park , BongJin Son , Jangwoo Lee
IPC: H01L23/373 , H01L23/367 , H01L21/56 , H01L25/10 , H01L25/00 , H01L25/065 , H01L23/498 , H01L23/50 , H01L23/00
Abstract: Provided are a thermal interface material layer and a package-on-package device including the same. The package-on-package device may include a thermal interface material layer interposed between lower and upper semiconductor packages and configured to have a specific physical property. Accordingly, it is possible to prevent a crack from occurring in a lower semiconductor chip, when a solder ball joint process is performed to mount the upper semiconductor package on the lower semiconductor package.
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公开(公告)号:US20180145006A1
公开(公告)日:2018-05-24
申请号:US15856800
申请日:2017-12-28
Applicant: Samsung Electronics Co., Ltd.
Inventor: Min-Ok NA , Jongkook Kim , Hyo-Chang Ryu , Jin-woo Park , BongJin Son , Jangwoo Lee
IPC: H01L23/373 , H01L23/367 , H01L21/56 , H01L25/10 , H01L25/00 , H01L25/065 , H01L23/00 , H01L23/50 , H01L23/498
CPC classification number: H01L23/373 , H01L21/563 , H01L23/367 , H01L23/49827 , H01L23/50 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/92 , H01L25/065 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45015 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/92225 , H01L2225/0651 , H01L2225/06568 , H01L2225/1023 , H01L2225/1058 , H01L2225/107 , H01L2225/1094 , H01L2924/00014 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/18161 , H01L2924/00012 , H01L2924/00 , H01L2924/207
Abstract: Provided are a thermal interface material layer and a package-on-package device including the same. The package-on-package device may include a thermal interface material layer interposed between lower and upper semiconductor packages and configured to have a specific physical property. Accordingly, it is possible to prevent a crack from occurring in a lower semiconductor chip, when a solder ball joint process is performed to mount the upper semiconductor package on the lower semiconductor package.
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公开(公告)号:US11562780B2
公开(公告)日:2023-01-24
申请号:US17411421
申请日:2021-08-25
Applicant: Samsung Electronics Co., Ltd.
Inventor: Byunghoon Jeong , Kyungtae Kang , Jangwoo Lee , Jeongdon Ihm
IPC: G11C7/22 , G11C7/10 , H03K19/173 , G11C8/18 , G11C29/42
Abstract: A memory device includes a memory cell array configured to store data; and a data output circuit configured to transmit status data to an external device through at least one data line in a latency period in response to a read enable signal received from the external device and transmit the data read from the memory cell array to the external device through the at least one data line in a period subsequent to the latency period.
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公开(公告)号:US11336266B2
公开(公告)日:2022-05-17
申请号:US17222033
申请日:2021-04-05
Applicant: Samsung Electronics Co., Ltd.
Inventor: Dongho Shin , Kyungtae Kang , Junha Lee , Tongsung Kim , Jangwoo Lee , Jeongdon Ihm , Byunghoon Jeong
Abstract: A method of operating a system including a parameter monitoring circuit and a host, includes generating a first parameter applying a first code to a current parameter, wherein a first offset is applied to the first code; generating a first comparison result by comparing the first parameter with a reference parameter value; generating a second parameter applying a second code to the current parameter, wherein a second offset is applied to the second code; generating a second comparison result by comparing the second parameter with the reference parameter value; detecting an error in the current parameter, based on the first comparison result and the second comparison result; and providing a signal based on the error to the host.
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公开(公告)号:US11315614B2
公开(公告)日:2022-04-26
申请号:US17150307
申请日:2021-01-15
Applicant: Samsung Electronics Co., Ltd.
Inventor: Daehoon Na , Jeongdon Ihm , Jangwoo Lee , Byunghoon Jeong
Abstract: A memory system includes a memory device including a plurality of non-volatile memories and an interface circuit connected to each of the plurality of non-volatile memories, and a memory controller connected to the interface circuit and configured to transmit/receive data according to a first clock, wherein the interface circuit is configured to divide the first clock into a second clock, according to the number of the plurality of non-volatile memories, and transmit/receive data to/from each of the plurality of non-volatile memories, according to the second clock.
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公开(公告)号:US11199975B2
公开(公告)日:2021-12-14
申请号:US16861802
申请日:2020-04-29
Applicant: Samsung Electronics Co., Ltd.
Inventor: Daehoon Na , Jangwoo Lee , Jeongdon Ihm
Abstract: An interface circuit of a memory device including a plurality of memory dies including a plurality of registers corresponding to the plurality of memory dies, respectively, the plurality of registers each configured to store command information related to a data operation command, a demultiplexer circuit configured to provide input command information to a selected register from among the plurality of registers according to at least one of a first address or a first chip selection signal, the input command information being received from outside the interface circuit, and a multiplexer circuit configured to receive output command information from the selected register from among the plurality of registers and output the output command information according to at least one of a second address or a second chip selection signal may be provided.
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公开(公告)号:US20200006188A1
公开(公告)日:2020-01-02
申请号:US16566380
申请日:2019-09-10
Applicant: Samsung Electronics Co., Ltd.
Inventor: Min-Ok Na , Jongkook Kim , Hyo-Chang Ryu , Jin-woo Park , BongJin Son , Jangwoo Lee
IPC: H01L23/373 , H01L23/367 , H01L21/56 , H01L25/10 , H01L25/00 , H01L25/065
Abstract: Provided are a thermal interface material layer and a package-on-package device including the same. The package-on-package device may include a thermal interface material layer interposed between lower and upper semiconductor packages and configured to have a specific physical property. Accordingly, it is possible to prevent a crack from occurring in a lower semiconductor chip, when a solder ball joint process is performed to mount the upper semiconductor package on the lower semiconductor package.
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