公开(公告)号：US20230386542A1

公开(公告)日：2023-11-30

申请号：US18447950

申请日：2023-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JIN-HOON JANG ,  KYUNGRYUN KIM ,  YOUNG JU KIM ,  SEUNG-JUN LEE ,  YOUNGBIN LEE ,  YEONKYU CHOI

IPC: G11C8/18 ,  G11C7/10

CPC classification number: G11C8/18 ,  G11C7/1045 ,  G11C7/1093 ,  G11C7/1066

Abstract: Disclosed is an operating method of a memory device communicating with a memory controller, which includes receiving a first command from the memory controller, the first command indicating initiation of synchronization of a data clock signal and defining a clock section corresponding to the synchronization, preparing a toggling of the data clock signal during a preparation time period, processing a first data stream based on the data clock signal toggling at a reference frequency, and processing a second data stream based on the data clock toggling at the reference frequency and extended for a period of the defined first clock section.

公开(公告)号：US20220293154A1

公开(公告)日：2022-09-15

申请号：US17496003

申请日：2021-10-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JIN-HOON JANG ,  KYUNGRYUN KIM ,  YOUNG JU KIM ,  SEUNG-JUN LEE ,  YOUNGBIN LEE ,  YEONKYU CHOI

IPC: G11C8/18 ,  G11C7/10

Abstract: Disclosed is an operating method of a memory device communicating with a memory controller, which includes receiving a first command from the memory controller, the first command indicating initiation of synchronization of a data clock signal and defining a clock section corresponding to the synchronization, preparing a toggling of the data clock signal during a preparation time period, processing a first data stream based on the data clock signal toggling at a reference frequency, and processing a second data stream based on the data clock toggling at the reference frequency and extended for a period of the defined first clock section.

公开(公告)号：US20190139594A1

公开(公告)日：2019-05-09

申请号：US16032822

申请日：2018-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-Woo RYU ,  KYUNGRYUN KIM ,  SOO HWAN KIM ,  HUIKAP YANG

IPC: G11C11/4091 ,  G11C8/08 ,  G11C7/18 ,  G11C11/4097 ,  G11C11/4093 ,  G11C7/06

CPC classification number: G11C11/4091 ,  G11C5/025 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1042 ,  G11C7/1048 ,  G11C7/18 ,  G11C8/08 ,  G11C11/4085 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2207/002

Abstract: A semiconductor memory device includes a cell array that includes a first row block and a second row block, a bit line sense amplifier block that senses data stored in the first row block or the second row block, a local sense amplifier that latches the sensed data transferred from the bit line sense amplifier block, and a switch that connects the local sense amplifier with a selected one of a first global data line and a second global data line in response to a select signal. The second row block may be placed at an edge of the cell array, and the switch connects the local sense amplifier with the first global data line when the first row block is activated and connects the local sense amplifier with the second global data line when the second row block is activated.

公开(公告)号：US20160351266A1

公开(公告)日：2016-12-01

申请号：US15232909

申请日：2016-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNGRYUN KIM ,  SANGYONG YOON ,  KIWHAN SONG

IPC: G11C16/28 ,  G06F3/06 ,  G11C16/30 ,  G11C16/32 ,  G11C16/10

CPC classification number: G11C16/28 ,  G06F3/0604 ,  G06F3/0629 ,  G06F3/0679 ,  G11C7/227 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3459 ,  G11C2211/5621

Abstract: A nonvolatile memory system includes a nonvolatile memory device including a plurality of memory cells, and a memory controller. The memory controller is configured to count a clock to generate a current time, program dummy data at predetermined memory cells among the plurality of memory cells at a power-off state, detect a charge loss of the predetermined memory cells when a power-on state occurs after the power-off state, and restore the current time based on the detected charge loss.

公开(公告)号：US20150135025A1

公开(公告)日：2015-05-14

申请号：US14523978

申请日：2014-10-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNGRYUN KIM ,  SEOKJUN HAM

IPC: G06F11/10 ,  G11C29/52 ,  G06F12/02 ,  G06F11/07

CPC classification number: G06F12/0246 ,  G06F11/1048 ,  G06F2212/7211 ,  G11C29/52 ,  G11C2029/4402

Abstract: A method is for driving a memory controller which is configured to control a nonvolatile memory device. The method includes counting a number of error bits of read data provided from the nonvolatile memory device, determining a running average value using the number of error bits; and performing a wear leveling on the nonvolatile memory device using the running average value as a wear leveling index.

Abstract translation: 一种用于驱动被配置为控制非易失性存储器件的存储器控​​制器的方法。 该方法包括对从非易失性存储器件提供的读取数据的错误位数进行计数，使用错误位数确定运行平均值; 以及使用所述运行平均值作为磨损均衡指数，在所述非易失性存储装置上进行磨损均衡。

公开(公告)号：US20150039809A1

公开(公告)日：2015-02-05

申请号：US14299505

申请日：2014-06-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SIHWAN KIM ,  SANGYONG YOON ,  KYUNGRYUN KIM

IPC: G11C16/34 ,  G11C11/406

CPC classification number: G11C16/3404 ,  G11C16/0483 ,  G11C16/10

Abstract: A program method for a nonvolatile memory system including a reprogram operation that does not require a reload of first program data to page buffers of a constituent nonvolatile memory device between execution of a first coarse program step and execution of a first fine program step being performed after the execution of an intervening second coarse program step.

Abstract translation: 一种非易失性存储器系统的程序方法，包括：在执行第一粗略程序步骤和执行第一精细程序步骤之后执行第一程序数据的第一程序数据不需要重新加载组成非易失性存储器件的页面缓冲器的再编程操作， 执行中间的第二粗程序步骤。

公开(公告)号：US20240329045A1

公开(公告)日：2024-10-03

申请号：US18742453

申请日：2024-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JIN-HOON JANG ,  KYUNGRYUN KIM ,  YOUNG JU KIM ,  SEUNG-JUN LEE ,  YOUNGBIN LEE ,  YEONKYU CHOI

IPC: G01N33/574 ,  G01N33/50

CPC classification number: G01N33/574 ,  G01N33/5091

Abstract: Disclosed is an operating method of a memory device communicating with a memory controller, which includes receiving a first command from the memory controller, the first command indicating initiation of synchronization of a data clock signal and defining a clock section corresponding to the synchronization, preparing a toggling of the data clock signal during a preparation time period, processing a first data stream based on the data clock signal toggling at a reference frequency, and processing a second data stream based on the data clock toggling at the reference frequency and extended for a period of the defined first clock section.