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    Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices
    1.
    发明授权
    Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices 有权

    公开(公告)号：US10573356B2

    公开(公告)日：2020-02-25

    申请号：US15851197

    申请日：2017-12-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Uhn Cha ,  Young-Hun Seo ,  Kwang-Il Park ,  Seung-Jun Bae

    IPC: G06F11/00 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4096 ,  H03M13/00 ,  G06F11/10

    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes bank arrays, each of the bank arrays includes a first sub array and a second sub array, and each of the first sub array and the second sub array includes a normal cell region to store data bits and a parity cell region to store parity bits. The ECC engine generates the parity bits and corrects error bit. The I/O gating circuit is connected between the ECC engine and the memory cell array. The control logic circuit controls the I/O gating circuit to perform column access to the normal cell region according to a multiple of a burst length and to perform column access to the parity cell region according to a non-multiple of the burst length partially.

    Semiconductor memory devices and memory systems including the same
    2.
    发明授权
    Semiconductor memory devices and memory systems including the same 有权
    半导体存储器件和包括其的存储器系统

    公开(公告)号：US09552867B2

    公开(公告)日：2017-01-24

    申请号：US14588496

    申请日：2015-01-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young-Soo Sohn ,  Uk-Song Kang ,  Kwang-Il Park ,  Chul-Woo Park ,  Hak-Soo Yu ,  Jae-Youn Youn

    IPC: G06F3/06 ,  G11C11/408 ,  G11C5/02 ,  G11C7/02

    CPC classification number: G11C11/4087 ,  G11C5/025 ,  G11C7/02 ,  G11C11/4085

    Abstract: A semiconductor memory device includes a control logic and a memory cell array in which a plurality of memory cells are arranged. The memory cell array includes a plurality of bank arrays, and each of the plurality of bank arrays includes a plurality of sub-arrays. The control logic controls an access to the memory cell array based on a command and an address signal. The control logic dynamically sets a keep-away zone that includes a plurality of memory cell rows which are deactivated based on a first word-line when the first word-line is enabled. The first word-line is coupled to a first memory cell row of a first sub-array of the plurality of sub-arrays. Therefore, increased timing parameters may be compensated, and parallelism may be increased.

    Abstract translation: 半导体存储器件包括控制逻辑和其中布置有多个存储器单元的存储单元阵列。 存储单元阵列包括多个存储体阵列，并且多个存储体阵列中的每一个包括多个子阵列。 控制逻辑基于命令和地址信号控制对存储器单元阵列的访问。 控制逻辑动态地设置包括在第一字线被启用时基于第一字线被去激活的多个存储器单元行的保留区。 第一字线耦合到多个子阵列中的第一子阵列的第一存储单元行。 因此，可以补偿增加的定时参数，并且可以增加并行性。

    Semiconductor memory devices and memory systems including the same
    5.
    发明授权
    Semiconductor memory devices and memory systems including the same 有权
    半导体存储器件和包括其的存储器系统

    公开(公告)号：US09390778B2

    公开(公告)日：2016-07-12

    申请号：US14798164

    申请日：2015-07-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Su-A Kim ,  Dae-Sun Kim ,  Dae-Jeong Kim ,  Sung-Min Ryu ,  Kwang-Il Park ,  Chul-Woo Park ,  Young-Soo Sohn ,  Jae-Youn Youn

    IPC: G11C8/12 ,  G11C8/08 ,  G11C7/02 ,  G11C7/18 ,  G11C7/10

    CPC classification number: G11C8/08 ,  G11C5/025 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/18 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4097

    Abstract: A semiconductor memory device includes a memory cell array, sub word-line drivers and power selection switches. The memory cell array includes memory cell rows coupled to word lines. The sub word line drivers are coupled to the word lines. The power selection switches are coupled to the sub word-line drivers. Each power selection switch controls a deactivation voltage level of a first word-line activated from the word-lines and an off-voltage level of a second word line adjacent to the first word line so that the deactivation voltage level and the off-voltage level have at least one of a ground voltage, a first negative voltage and a second negative voltage. The ground voltage, the first negative voltage and the second negative voltage have different voltage levels from each other.

    Abstract translation: 半导体存储器件包括存储单元阵列，子字线驱动器和功率选择开关。 存储单元阵列包括耦合到字线的存储单元行。 子字线驱动器耦合到字线。 功率选择开关耦合到子字线驱动器。 每个电源选择开关控制从字线激活的第一字线的去激活电压电平和与第一字线相邻的第二字线的截止电压电平，使得去激活电压电平和截止电压电平 具有接地电压，第一负电压和第二负电压中的至少一个。 接地电压，第一负电压和第二负电压彼此具有不同的电压电平。

    Memory systems that adjust an auto-refresh operation responsive to a self-refresh operation history
    7.
    发明授权
    Memory systems that adjust an auto-refresh operation responsive to a self-refresh operation history 有权

    公开(公告)号：US09767050B2

    公开(公告)日：2017-09-19

    申请号：US15065211

    申请日：2016-03-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Su-Yeon Doo ,  Tae-Young Oh ,  Kwang-Il Park

    IPC: G11C7/00 ,  G06F13/16 ,  G11C11/406

    CPC classification number: G06F13/1636 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/40615

    Abstract: A memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a plurality of dynamic memory cells. The memory controller controls the semiconductor memory device. The memory controller applies an auto-refresh command to the semiconductor memory device at each refresh interval of the semiconductor memory device such that the semiconductor memory performs a refresh operation in a normal mode, and does not apply the auto-refresh command to the semiconductor memory device during a self-refresh interval in which the semiconductor memory performs a self-refresh operation. After the semiconductor memory device exits from the self-refresh interval, the memory controller adjusts an application of the auto-refresh command in the normal mode by reflecting information of the self-refresh interval.

    Memory device and memory system having the same
    9.
    发明授权
    Memory device and memory system having the same 有权

    公开(公告)号：US09685218B2

    公开(公告)日：2017-06-20

    申请号：US15236895

    申请日：2016-08-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young-Soo Sohn ,  Chul-Woo Park ,  Si-Hong Kim ,  Kwang-Il Park ,  Jae-Youn Youn

    IPC: G11C7/10 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/408

    CPC classification number: G11C11/406 ,  G11C11/4076 ,  G11C11/4087

    Abstract: A memory device includes a memory cell array, an intensively accessed row detection circuit, and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The intensively accessed row detection circuit generates an intensively accessed row address indicating an intensively accessed memory cell row among the plurality of memory cell rows based on an accumulated access time for each of the plurality of memory cell rows. The refresh control unit preferentially refreshes neighboring memory cell rows adjacent to the intensively accessed memory cell row indicated by the intensively accessed row address when receiving the intensively accessed row address from the intensively accessed row detection unit. The memory device effectively reduces a rate of data loss.

    Memory device and memory system having the same
    10.
    发明授权
    Memory device and memory system having the same 有权
    存储器件和存储器系统具有相同的功能

    公开(公告)号：US09536586B2

    公开(公告)日：2017-01-03

    申请号：US14514416

    申请日：2014-10-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young-Soo Sohn ,  Chul-Woo Park ,  Si-Hong Kim ,  Kwang-Il Park ,  Jae-Youn Youn

    IPC: G11C7/10 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4076

    CPC classification number: G11C11/406 ,  G11C11/4076 ,  G11C11/4087

    Abstract: A memory device includes a memory cell array, an intensively accessed row detection circuit, and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The intensively accessed row detection circuit generates an intensively accessed row address indicating an intensively accessed memory cell row among the plurality of memory cell rows based on an accumulated access time for each of the plurality of memory cell rows. The refresh control unit preferentially refreshes neighboring memory cell rows adjacent to the intensively accessed memory cell row indicated by the intensively accessed row address when receiving the intensively accessed row address from the intensively accessed row detection unit. The memory device effectively reduces a rate of data loss.

    Abstract translation: 存储器件包括存储单元阵列，集中访问的行检测电路和刷新控制电路。 存储单元阵列包括多个存储单元行。 集中访问的行检测电路基于多个存储单元行中的每一个的累积访问时间，生成指示多个存储单元行中的集中访问的存储单元行的集中访问的行地址。 当从集中访问的行检测单元接收到集中访问的行地址时，刷新控制单元优先刷新与由强行访问的行地址指示的集中访问的存储单元行相邻的相邻存储单元行。 存储器件有效地降低了数据丢失率。

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