公开(公告)号：US20240159657A1

公开(公告)日：2024-05-16

申请号：US18202663

申请日：2023-05-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sejin OH ,  Sunggil KANG ,  Sangki NAM ,  Jeongmin BANG ,  Dougyong SUNG ,  Yeongkwang LEE ,  Sungho JANG ,  Jonghun PI

IPC: G01N21/25 ,  G01N21/31 ,  H01L21/67

CPC classification number: G01N21/255 ,  G01N21/3103 ,  H01L21/67069 ,  G01N2201/061 ,  G01N2201/062

Abstract: Provided is an apparatus configured to measure radical spatial density distribution including a process chamber including a viewport, a driving device configured to move a moving wall inside the process chamber, a light source configured to generate light, a collimator disposed in the viewport of the process chamber and configured to transmit light received from the light source to the moving wall and receive light reflected from the moving wall, and a spectrometer configured to receive the reflected light from the collimator, and measure radical spatial density based on analyzing an absorption amount of a spectrum of the received light.

公开(公告)号：US20240060185A1

公开(公告)日：2024-02-22

申请号：US18231400

申请日：2023-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeontae KIM ,  Yihwan KIM ,  Hunyong PARK ,  Keesoo PARK ,  Janghwi LEE ,  Sungho JANG

IPC: C23C16/48 ,  C23C16/458

CPC classification number: C23C16/482 ,  C23C16/4585

Abstract: A substrate processing apparatus includes a chamber including a susceptor to support a substrate, a reflective housing outside the chamber, a light source in the reflective housing, the light source being configured to emit a light toward the susceptor, and a light adjuster between the light source and the susceptor, the light adjuster including a support portion supported inside the chamber and a lens coupled to the support portion, and the lens including a transmission portion configured to transmit the light and a scattering pattern portion configured to scatter the light.

公开(公告)号：US20200319025A1

公开(公告)日：2020-10-08

申请号：US16751356

申请日：2020-01-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongsu KIM ,  Younghwan KIM ,  Junbum PARK ,  Youngjoo LEE ,  Sungho JANG

IPC: G01J3/02 ,  G01J3/10 ,  G02B27/14

Abstract: An optical emission spectroscopy (OES) calibration system includes a chamber, an adapter, an OES device, a calibration device, and a spectrometer. The chamber includes a viewport. The adapter is fastened to the viewport, and includes a first beam splitter and a second beam splitter. The OES device detects plasma light generated in the chamber and transmitted through the adapter and generates OES data based on the detected plasma light. The calibration device includes a light source, and generates correction data for compensating for deviations in the OES data. The spectrometer detects light emitted from the light source and split by the first beam splitter or the second beam splitter. Each of the OES device, the calibration device, and the spectrometer is fastened to the adapter through an optical cable, and the calibration device generates the correction data using an intensity of light detected by the spectrometer.

公开(公告)号：US20240268103A1

公开(公告)日：2024-08-08

申请号：US18511000

申请日：2023-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junsoo KIM ,  Sungho JANG

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/315 ,  H10B12/482

Abstract: A semiconductor device includes a first active pattern protruding from a substrate and extending in a first direction parallel to an upper surface of the substrate; first and second recesses crossing the first active pattern in a second direction perpendicular to the first direction; a first gate structure in the first recess, and including a first gate oxide layer, a first gate pattern and a first capping pattern; a second gate structure in the second recess, and including a second gate oxide layer, a second gate pattern and a second capping pattern; a first metal liner pattern surrounding a portion of a sidewall of the first active pattern, and directly contacting a sidewall of the first gate pattern; and a second metal liner pattern surrounding a portion of the sidewall of the first active pattern, and directly contacting a sidewall of the second gate pattern.

公开(公告)号：US20230187235A1

公开(公告)日：2023-06-15

申请号：US18073980

申请日：2022-12-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Akinori OKUBO ,  Youngchul KWON ,  Sungho JANG ,  Jungchul LEE ,  Deoksuk JANG

IPC: H01L21/67 ,  G02B27/09 ,  G02B27/00 ,  B23K26/53

CPC classification number: H01L21/67092 ,  G02B27/0927 ,  G02B27/0081 ,  B23K26/53 ,  G02B19/0047

Abstract: A stealth dicing laser device including: a pulse laser generator configured to generate laser light; a condenser lens formed in an optical path of the laser light; a pupil filter configured to transform a phase of the laser light before the laser light passes through the condenser lens; and a controller configured to provide a phase control signal to the pupil filter, wherein the pupil filter transforms the phase of the laser light based on the phase control signal, wherein the phase control signal is a signal transforming a phase expression of the laser light based on a parameter.

公开(公告)号：US20220351947A1

公开(公告)日：2022-11-03

申请号：US17548775

申请日：2021-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kuihyun YOON ,  Sang Ki NAM ,  Kwonsang SEO ,  Sungho JANG ,  Jungmin KO ,  Nam Kyun KIM ,  Tae-Hyun KIM ,  Seunghan BAEK ,  Seungbin AHN ,  Jungmo YANG ,  Changheon LEE ,  Kangmin JEON

IPC: H01J37/32

Abstract: A plasma confinement ring includes a lower ring, an upper ring on the lower ring, and a connection ring extended to connect the lower ring to the upper ring. The lower ring includes a lower center hole vertically penetrating the lower ring at a center of the lower ring and at least one slit penetrating the lower ring in a region outside the lower center hole. The slit is structured to pass a more amount of air or gas at a first portion closer to the center of the lower ring than at a second portion farther from the center of the lower ring.

公开(公告)号：US20250014871A1

公开(公告)日：2025-01-09

申请号：US18406898

申请日：2024-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungwon CHO ,  Kyunghyun KIM ,  Ingi KIM ,  Sangki NAM ,  Dougyong SUNG ,  Sejin OH ,  Sungho JANG

IPC: H01J37/32 ,  H01L21/683

Abstract: According to an aspect of the present inventive concepts, a semiconductor processing apparatus includes: a chamber; an electrostatic chuck in an internal space of the chamber; a plurality of grid electrodes installed on the electrostatic chuck so as to be separated from each other in a first direction, perpendicular to an upper surface of the electrostatic chuck, and respectively having a plurality of through-holes; a plurality of reflectors between the plurality of grid electrodes and the electrostatic chuck and reflecting ions passing through the plurality of through-holes in each of the plurality of grid electrodes; and a voltage supply unit outputting a bias voltage having a predetermined cycle to at least one of the plurality of grid electrodes, wherein each of the plurality of grid electrodes includes a base plate containing a conductive material, and a cover layer covering a surface of the base plate and containing a metal oxide.

公开(公告)号：US20180158871A1

公开(公告)日：2018-06-07

申请号：US15653198

申请日：2017-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Chan-Sic YOON ,  Augustin HONG ,  Keunnam KIM ,  Dongoh KIM ,  Bong-Soo KIM ,  Jemin PARK ,  Hoin LEE ,  Sungho JANG ,  Kiwook JUNG ,  Yoosang HWANG

IPC: H01L27/24 ,  H01L27/22 ,  H01L27/108

CPC classification number: H01L27/10894 ,  H01L27/10823 ,  H01L27/10844 ,  H01L27/10876 ,  H01L27/10897 ,  H01L27/228 ,  H01L27/2436

Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

公开(公告)号：US20150303201A1

公开(公告)日：2015-10-22

申请号：US14591165

申请日：2015-01-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjin LEE ,  Sungho JANG ,  Jiyoung KIM ,  Kang-Uk KIM ,  Chan Min LEE ,  Juyeon JANG

IPC: H01L27/108 ,  H01L21/768 ,  H01L21/285 ,  H01L21/311

CPC classification number: H01L27/10885 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/32139 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897

Abstract: Semiconductor devices, and methods for forming the same, include forming a first wiring film and an etching buffer film in a cell array region and a peripheral circuit region of a substrate, and forming a contact hole by selectively etching the etching buffer film and the first wiring film so as to expose an active region of the cell array region and at least a part of a field isolation region adjacent thereto. A bit line contact is formed in the contact hole to be in contact with the active region, and a second wiring film is formed over the substrate. By patterning the second wiring film, the bit line contact, the etching buffer film, and the first wiring film, a bit line is formed in the cell array region and a peripheral gate is formed in the peripheral circuit region.

Abstract translation: 半导体器件及其形成方法包括在基板的单元阵列区域和外围电路区域中形成第一布线膜和蚀刻缓冲膜，并且通过选择性蚀刻蚀刻缓冲膜和第一布线膜形成接触孔 布线膜以暴露电池阵列区域的有源区域和与其相邻的场隔离区域的至少一部分。 在接触孔中形成与有源区接触的位线接触，在基板上形成第二布线膜。 通过图案化第二布线膜，位线接触，蚀刻缓冲膜和第一布线膜，在单元阵列区域中形成位线，并且在外围电路区域中形成周边栅极。

公开(公告)号：US20140264517A1

公开(公告)日：2014-09-18

申请号：US14175076

申请日：2014-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngkuk KIM ,  Ho-Kyun AN ,  Jaehyun YEO ,  Badro IM ,  HanJin LIM ,  Sungho JANG ,  Insang JEON

IPC: H01L27/108 ,  H01L27/105

CPC classification number: H01L27/10894 ,  H01L21/823412 ,  H01L21/823462 ,  H01L27/10814 ,  H01L27/10861

Abstract: Semiconductor devices having a silicon-germanium channel layer and methods of forming the semiconductor devices are provided. The methods may include forming a silicon-germanium channel layer on a substrate in a peripheral circuit region and sequentially forming a first insulating layer and a second insulating layer on the silicon-germanium channel layer. The methods may also include forming a conductive layer on the substrate, which includes a cell array region and the peripheral circuit region, and patterning the conductive layer to form a conductive line in the cell array region and a gate electrode in the peripheral circuit region. The first insulating layer may be formed at a first temperature and the second insulating layer may be formed at a second temperature higher than the first temperature.

Abstract translation: 提供具有硅 - 锗沟道层的半导体器件和形成半导体器件的方法。 所述方法可以包括在外围电路区域中的衬底上形成硅 - 锗沟道层，并且在硅 - 锗沟道层上依次形成第一绝缘层和第二绝缘层。 该方法还可以包括在衬底上形成导电层，该导电层包括电池阵列区域和外围电路区域，以及图案化导电层以在电池阵列区域中形成导线以及在外围电路区域中形成栅极电极。 第一绝缘层可以在第一温度下形成，并且第二绝缘层可以在高于第一温度的第二温度下形成。