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公开(公告)号：US20250103091A1
公开(公告)日：2025-03-27
申请号：US18756305
申请日：2024-06-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Tongsung KIM , Woojung KIM , Yoonji PARK , Younghoon SON , Seonkyoo LEE , Ilyoung JIN
Abstract: Provided are an apparatus and a method for adjusting a skew between data and a clock. The apparatus driven by a supply voltage includes a clock circuit that adjusts a skew between data and a clock. The clock circuit performs a first loop operation through a first loop and a second loop operation through a second loop, based on a phase difference between data and a clock. The first loop operation is performed until there is no phase difference between the data and the clock, and the second loop operation is performed until a first slope representing a change in delay of the data with respect to the levels of the power voltage and a second slope representing a change in delay of the clock become identical to each other.
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公开(公告)号：US20240221795A1
公开(公告)日：2024-07-04
申请号：US18231935
申请日：2023-08-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngwoo PARK , Tongsung KIM , Youngmin KIM , Seungjin PARK , Seunghoon LEE , Chaekang LIM , Youngchul CHO , Youngdon CHOI , Junghwan CHOI
CPC classification number: G11C7/1048 , H03F3/45475 , H03K5/24 , H03M1/0607 , H03F2200/375 , H03F2203/45044 , H03F2203/45212
Abstract: A data converter including an autozeroing circuit including a plurality of gain circuits having a first amplification circuit and a first capacitor connected to the first amplification circuit, the first amplification circuit performing a switch feedthrough offset cancellation operation of storing an offset voltage of the autozeroing circuit in the capacitor through a switch, a comparator circuit including a first input terminal and a second input terminal, the comparator circuit comparing a first input terminal voltage level of the first input terminal with a second input terminal voltage level of the second input terminal, a first switch unit connected between the autozeroing circuit and the comparator circuit, the first switch disconnecting the autozeroing circuit from the comparator circuit during the switch feedthrough offset cancellation operation of the autozeroing circuit, and a second switch unit connected between a first input signal line and a second input signal line.
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公开(公告)号：US20240212729A1
公开(公告)日：2024-06-27
申请号：US18392199
申请日：2023-12-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Tongsung KIM , Seonkyoo LEE , Seungjun BAE , Taesung LEE
CPC classification number: G11C7/222 , G11C7/1066
Abstract: A storage device includes a first chip and a second chip configured to exchange data with the first chip. The first chip may transmit a data strobe signal and a plurality of data signals, applied with different delay times, to the second chip. The second chip may sample the plurality of data signals, applied with the different delay times, using the data strobe signal received from the first chip during data training.
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公开(公告)号：US20210359684A1
公开(公告)日：2021-11-18
申请号：US17389148
申请日：2021-07-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Tongsung KIM , Youngmin JO , Jungjune PARK , Jindo BYUN , Dongho SHIN , Jeongdon IHM
IPC: H03K19/00 , H03K19/0185 , G11C7/10 , G11C8/10 , H03K19/08
Abstract: An impedance calibration circuit includes a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor; a second code generation circuit configured to form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and generate a second code by using the second reference resistor; and a target impedance code generation circuit configured to generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.
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公开(公告)号：US20250123776A1
公开(公告)日：2025-04-17
申请号：US18999741
申请日：2024-12-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngmin JO , Tongsung KIM , Chiweon YOON , Seonkyoo LEE , Byunghoon JEONG
Abstract: A method of operating a storage device including first and second memory devices and a memory controller, which are connected to a single channel, the method including: transmitting first data output from the first memory device to the memory controller through a data signal line in the single channel; and transmitting a command to the second memory device through the data signal line while the memory controller receives the first data, wherein a voltage level of the data signal line is based on the command and the first data of the first memory device is loaded on the data signal line, and the first data and the command are transmitted in both directions of the data signal line.
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Patent Agency Ranking
公开(公告)号：US20220229599A1
公开(公告)日：2022-07-21
申请号：US17528285
申请日：2021-11-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngmin JO , Tongsung KIM , Chiweon YOON , Seonkyoo LEE , Byunghoon JEONG
Abstract: A method of operating a storage device including first and second memory devices and a memory controller, which are connected to a single channel, the method including: transmitting first data output from the first memory device to the memory controller through a data signal line in the single channel; and transmitting a command to the second memory device through the data signal line while the memory controller receives the first data, wherein a voltage level of the data signal line is based on the command and the first data of the first memory device is loaded on the data signal line, and the first data and the command are transmitted in both directions of the data signal line.
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公开(公告)号：US20210242870A1
公开(公告)日：2021-08-05
申请号：US17021728
申请日：2020-09-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Tongsung KIM , Youngmin JO , Jungjune PARK , Jindo BYUN , Dongho SHIN , Jeongdon IHM
IPC: H03K19/00 , H03K19/0185 , H03K19/08 , G11C7/10 , G11C8/10
Abstract: An impedance calibration circuit includes a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor; a second code generation circuit configured to form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and generate a second code by using the second reference resistor; and a target impedance code generation circuit configured to generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.
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公开(公告)号：US20240096382A1
公开(公告)日：2024-03-21
申请号：US18464618
申请日：2023-09-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Tongsung KIM , Junghwan KWAK , Seungjun BAE , Chiweon YOON , Byungkwan CHUN , Youngmin JO
CPC classification number: G11C7/1048 , G06F13/16 , G06F2213/16 , G11C2207/2254
Abstract: A ZQ calibration circuit includes: a ZQ controller configured to detect an end of one interface mode, among a plurality of interface modes in which ZQ calibration is supported, and to instruct a switch to another interface mode in response to the one interface mode coming to an end; a ZQ engine configured to generate a first reference voltage corresponding to the one interface mode through a multi-reference voltage generator, to generate a second reference voltage corresponding to the another interface mode in response to the switch to the another interface mode being instructed, to perform the ZQ calibration based on the first reference voltage or the second reference voltage, and to output a calibration code; and a ZQ driver configured to output an output signal through an input/output pad based on the calibration code.
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公开(公告)号：US20230170030A1
公开(公告)日：2023-06-01
申请号：US18160620
申请日：2023-01-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Tongsung KIM , Youngmin Jo , Chiweon Yoon
IPC: G11C16/32
CPC classification number: G11C16/32 , G11C16/0483
Abstract: A nonvolatile memory device includes a first memory chip and a second memory chip connected to a controller through the same channel. The first memory chip generates a first signal from a first internal clock signal based on a clock signal received from the controller. The second memory chip generates a second signal from a second internal clock signal based on the clock signal, and performs a phase calibration operation on the second signal on the basis of a phase of the first signal by delaying the second internal clock signal based on a phase difference between the first and second signals.
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公开(公告)号：US20210226613A1
公开(公告)日：2021-07-22
申请号：US17222033
申请日：2021-04-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dongho SHIN , Kyungtae KANG , Junha LEE , Tongsung KIM , Jangwoo LEE , Jeongdon IHM , Byunghoon JEONG
Abstract: A method of operating a system including a parameter monitoring circuit and a host, includes generating a first parameter applying a first code to a current parameter, wherein a first offset is applied to the first code; generating a first comparison result by comparing the first parameter with a reference parameter value; generating a second parameter applying a second code to the current parameter, wherein a second offset is applied to the second code; generating a second comparison result by comparing the second parameter with the reference parameter value; detecting an error in the current parameter, based on the first comparison result and the second comparison result; and providing a signal based on the error to the host.
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