公开(公告)号：US11791394B2

公开(公告)日：2023-10-17

申请号：US18053777

申请日：2022-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangjun Yun ,  Uihui Kwon ,  Seongnam Kim ,  Hyoshin Ahn

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: Provided are metal oxide field-effect transistor (MOSFET) devices having a metal gate structure, in which a work function of the metal gate structure is uniform along a length direction of a channel, and manufacturing methods thereof. The MOSFET devices include a semiconductor substrate, an active area on the semiconductor substrate and extending in a first direction, and a gate structure on the semiconductor substrate. The gate structure extends across the active area in a second direction that traverses the first direction and comprises a high-k layer, a first metal layer, a work function control (WFC) layer, and a second metal layer, which are sequentially stacked on the active area. A lower surface of the WFC layer may be longer than a first interface between a lower surface of the first metal layer and an upper surface of the high-k layer in the first direction.

公开(公告)号：US20200082051A1

公开(公告)日：2020-03-12

申请号：US16390087

申请日：2019-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Uihui Kwon ,  Weiyi Qi ,  Yang Lu ,  Saetbyeol Ahn ,  Takeshi Okagaki

IPC: G06F17/50 ,  G06N20/00

Abstract: A standard cell design system is provided. The standard cell design system includes at least one processor configured to implement: a control engine that determines planar parameters and vertical parameters of a target standard cell, a three-dimensional structure generating engine that generates a three-dimensional structure of the target standard cell based on the planar parameters and the vertical parameters, an extraction engine that extracts a standard cell model of the target standard cell from the three-dimensional structure, an assessment engine that performs a plurality of assessment operations based on the standard cell model, and an auto-optimizing engine that adjusts, based on a machine learning algorithm, the planar parameters and the vertical parameters based on results of the plurality of assessment operations.

公开(公告)号：US12261208B2

公开(公告)日：2025-03-25

申请号：US18538575

申请日：2023-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghee Park ,  Myunggil Kang ,  Uihui Kwon ,  Seungkyu Kim ,  Ahyoung Kim ,  Youngseok Song

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: An integrated circuit device includes a fin-type active region disposed on a substrate and extending in a first horizontal direction, a gate line disposed on the fin-type active region and extending in a second horizontal direction intersecting the first horizontal direction, the gate line including, a connection protrusion portion including a protrusion top surface at a first vertical level from the substrate, and a main gate portion including a recess top surface extending in the second horizontal direction from the connection protrusion portion, the recess top surface being at a second vertical level lower than the first vertical level, a gate contact disposed on the gate line and connected to the connection protrusion portion, a source/drain region disposed on the fin-type active region and disposed adjacent to the gate line, and a source/drain contact disposed on the source/drain region.

公开(公告)号：US09130040B2

公开(公告)日：2015-09-08

申请号：US14248594

申请日：2014-04-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JaeHoo Park ,  Daewon Ha ,  Uihui Kwon ,  Sung-Dae Suk

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L29/785 ,  H01L27/092 ,  H01L29/66795 ,  H01L29/7853

Abstract: Provided are a semiconductor device and a method of manufacturing the same. The method of manufacturing a semiconductor device includes forming an active fin on a substrate; oxidizing a portion of the active fin to form an insulating pattern between the active fin and the substrate; forming a first gate pattern on the substrate, wherein the first gate pattern crosses the active fin; exposing the substrate on both sides of the first gate pattern; and forming source/drain regions on the exposed substrate.

Abstract translation: 提供半导体器件及其制造方法。 制造半导体器件的方法包括：在衬底上形成有源散热片; 氧化活性鳍片的一部分以在活性鳍片和衬底之间形成绝缘图案; 在所述衬底上形成第一栅极图案，其中所述第一栅极图案与所述有源鳍片交叉; 在第一栅极图案的两侧上暴露衬底; 以及在暴露的衬底上形成源极/漏极区域。

公开(公告)号：US11972185B2

公开(公告)日：2024-04-30

申请号：US16919157

申请日：2020-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehee Choi ,  Udit Monga ,  Ken Machida ,  Uihui Kwon ,  Yonghee Park

IPC: G06F30/3308 ,  G06F119/04

CPC classification number: G06F30/3308 ,  G06F2119/04

Abstract: A method of estimating aging of an integrated circuit (IC) includes: obtaining a first process design kit (PDK) including a plurality of first device models corresponding to a plurality of devices provided by a process of fabricating the IC; obtaining values of aging parameters of device instances included in a netlist defining the IC, by performing a first circuit simulation based on the netlist and the first PDK; and obtaining aging data of the IC by performing a second circuit simulation based on the values of the aging parameters and the netlist, wherein each of the plurality of first device models includes at least one measurement command to be executed in the first circuit simulation to calculate an aging parameter.

公开(公告)号：US20220285511A1

公开(公告)日：2022-09-08

申请号：US17455681

申请日：2021-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghee Park ,  Munhyeon Kim ,  Uihui Kwon ,  Joohyung You ,  Daewon Ha

IPC: H01L29/423 ,  H01L29/786 ,  H01L27/088 ,  H01L29/417

Abstract: A semiconductor device includes active regions extending on a substrate in a first direction, gate structures intersecting the active regions and extending on the substrate in a second direction, source/drain regions in recess regions in which the active regions are recessed, on both sides of each of the gate structures, and contact plugs connected to the source/drain regions, wherein each of the source/drain regions include first and second epitaxial layers sequentially stacked on the active regions in the recess regions in a third direction perpendicular to an upper surface of the substrate, respectively, and wherein ratios of the first epitaxial layer thickness in the third direction to the second epitaxial layer thickness in the third direction are different in different ones of the source/drain regions.

公开(公告)号：US20200075656A1

公开(公告)日：2020-03-05

申请号：US16286897

申请日：2019-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wook Lee ,  Euiyoung Song ,  Kwanghee Lee ,  Uihui Kwon ,  Jae Ho Kim ,  Jungchak Ahn

IPC: H01L27/146 ,  G02B5/18

Abstract: An image sensor may include a semiconductor substrate having a light receiving surface thereon and a plurality of spaced-apart semiconductor photoelectric conversion regions at adjacent locations therein. A grating structure is provided on the light receiving surface. This grating structure extends opposite each of the plurality of spaced-apart photoelectric conversion regions. An optically-transparent layer is provided on the grating structure. This grating structure includes a plurality of spaced-apart grating patterns, which can have the same height and the same width. In addition, the grating patterns may be spaced apart from each other by a uniform distance. The grating structure is configured to selectively produce ±1 or higher order diffraction lights to the photoelectric conversion regions, in response to light incident thereon.

公开(公告)号：US09634092B2

公开(公告)日：2017-04-25

申请号：US15046455

申请日：2016-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna Kumar Bhuwalka ,  Zhenhua Wu ,  Uihui Kwon ,  Keunho Lee

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/78 ,  H01L29/786 ,  H01L29/10 ,  H01L29/417

CPC classification number: H01L29/0673 ,  H01L29/0676 ,  H01L29/1037 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7782 ,  H01L29/785 ,  H01L29/78696

Abstract: Provided is a finFET device. The finFET device may include an active region which protrudes vertically from a substrate, a channel region disposed on a center of the active region, a drain region disposed on one side surface of the channel region, and a source region disposed on the other side surface of the channel region, a gate insulating layer formed on two opposing side surfaces of the channel region and having a U-shaped cross-section, gate spacers formed on outer surfaces of the gate insulating layer, drain spacers formed on two opposing side surfaces of the drain region, and source spacers formed on two opposing side surfaces of the source region, and at least one of the two side surfaces of the drain region has a tapered part.

公开(公告)号：US20160086841A1

公开(公告)日：2016-03-24

申请号：US14711394

申请日：2015-05-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNGHYUN SONG ,  Hyeon Kyun Noh ,  Taeyong Kwon ,  Sangsu Kim ,  Shigenobu Maeda ,  Krishna Bhuwalka ,  Uihui Kwon ,  Keunho Lee ,  Wonsok Lee

IPC: H01L21/762 ,  H01L29/10 ,  H01L21/02 ,  H01L29/06 ,  H01L21/308 ,  H01L29/66

CPC classification number: H01L21/76224 ,  H01L21/3086 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method for forming a pattern of a semiconductor device and a semiconductor device formed using the same are provided. The method includes forming a buffer layer on a substrate, forming a channel layer on the buffer layer, forming support patterns penetrating the channel layer, and forming channel fin patterns and a buffer pattern by patterning the channel layer and the buffer layer. The channel layer includes a material of which a lattice constant is different from that of the buffer layer, and each of the channel fin patterns has both sidewalls that are in contact with the support patterns and are opposite to each other.

Abstract translation: 提供了一种用于形成半导体器件的图案的方法和使用其形成的半导体器件。 该方法包括在衬底上形成缓冲层，在缓冲层上形成沟道层，形成穿透沟道层的支撑图案，并通过图案化沟道层和缓冲层形成沟道鳍图案和缓冲图案。 沟道层包括晶格常数与缓冲层的晶格常数不同的材料，并且每个沟道鳍图案具有与支撑图案接触并且彼此相对的两个侧壁。

公开(公告)号：US20250098224A1

公开(公告)日：2025-03-20

申请号：US18967518

申请日：2024-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghee Park ,  Munhyeon Kim ,  Uihui Kwon ,  Joohyung You ,  Daewon Ha

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/417 ,  H01L29/786

Abstract: A semiconductor device includes active regions extending on a substrate in a first direction, gate structures intersecting the active regions and extending on the substrate in a second direction, source/drain regions in recess regions in which the active regions are recessed, on both sides of each of the gate structures, and contact plugs connected to the source/drain regions, wherein each of the source/drain regions include first and second epitaxial layers sequentially stacked on the active regions in the recess regions in a third direction perpendicular to an upper surface of the substrate, respectively, and wherein ratios of the first epitaxial layer thickness in the third direction to the second epitaxial layer thickness in the third direction are different in different ones of the source/drain regions.