公开(公告)号：US20210005551A1

公开(公告)日：2021-01-07

申请号：US16793366

申请日：2020-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jangho LEE ,  Jongmin Baek ,  Wookyung YOU ,  Kyu-Hee HAN ,  Suhyun Bark

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

Abstract: Disclosed is a semiconductor device comprising a substrate, a first dielectric layer on the substrate, a first lower conductive line in the first dielectric layer, an etch stop layer on the first dielectric layer, a via-structure that penetrates the etch stop layer and connects to the first lower conductive line, a second dielectric layer on the etch stop layer, and an upper conductive line that penetrates the second dielectric layer and connects to the via-structure. The first dielectric layer includes a dielectric pattern at a level higher than a top surface of the first lower conductive line. The upper conductive line is in contact with a top surface of the etch stop layer. The etch stop layer has at an upper portion a rounded surface in contact with the via-structure.

公开(公告)号：US20190206794A1

公开(公告)日：2019-07-04

申请号：US16296388

申请日：2019-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangho RHA ,  Jongmin BAEK ,  Wookyung YOU ,  Sanghoon AHN ,  Nae-In LEE

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L21/306 ,  H01L21/288 ,  H01L23/532 ,  H01L21/02 ,  H01L21/321

CPC classification number: H01L23/5283 ,  H01L21/02178 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/288 ,  H01L21/306 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.

公开(公告)号：US20240258204A1

公开(公告)日：2024-08-01

申请号：US18486853

申请日：2023-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeonggil KIM ,  Hoonseok SEO ,  Minchul AHN ,  Wookyung YOU ,  Woojin LEE ,  Junghwan CHUN

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device comprising: a substrate including an active region extending in a first direction; a gate structure extending in a second direction on the active region; source/drain regions on the active region and adjacent the gate structure; a backside insulating layer on a lower surface of the substrate; a vertical power structure between adjacent source/drain regions, wherein the vertical power structure extends through the substrate and the backside insulating layer and has an exposed lower surface exposed; an interlayer insulating layer on the backside insulating layer; a backside power structure that extends through the interlayer insulating layer and is connected to the vertical power structure; and a first alignment insulating layer between the backside insulating layer and the interlayer insulating layer, wherein the first alignment insulating layer has a first opening exposing the lower surface of the vertical power structure and contacts the backside power structure.

公开(公告)号：US20240145345A1

公开(公告)日：2024-05-02

申请号：US18209206

申请日：2023-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeonggil KIM ,  Hoon Seok SEO ,  Yungbae KIM ,  Wookyung YOU

IPC: H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes active patterns on a substrate, source/drain patterns, first and second separation structures, wherein adjacent source/drain patterns are interposed between the first and second separation structures, an interlayer insulating layer on the source/drain patterns and first and second separation structures, a through-via between the adjacent source/drain patterns, penetrating the interlayer insulating layer, and extending toward the substrate, wherein a top of the through-via is coplanar with a top of the interlayer insulating layer, a dielectric layer selectively on the top of the interlayer insulating layer, and opening the top of the through-via, a power via guided to connect to the top of the through-via by the dielectric layer, a power line on the power via and electrically connected to the through-via through the power via, a power delivery network layer on a bottom of the substrate, and a lower conductor under the through-via.

公开(公告)号：US20240234250A9

公开(公告)日：2024-07-11

申请号：US18320423

申请日：2023-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangkoo KANG ,  Wookyung YOU ,  Minjae KANG ,  Koungmin RYU ,  Hoonseok SEO ,  Woojin LEE ,  Junchae LEE

IPC: H01L23/48 ,  H01L21/762 ,  H01L21/768 ,  H01L27/088

CPC classification number: H01L23/481 ,  H01L21/76224 ,  H01L21/76898 ,  H01L27/088 ,  H01L29/66439

Abstract: An integrated circuit (IC) device includes a substrate, a pair of fin-type active regions protruding from the substrate to define a trench region on the substrate, the fin-type active regions extending in a first lateral direction, a pair of source/drain regions on the fin-type active regions, respectively, a device isolation film in the trench region, the device isolation film apart from the substrate in a vertical direction, an etch stop structure filling at least a portion of the trench region between the substrate and the device isolation film, a via power rail between the pair of fin-type active regions and between the pair of source/drain regions, the via power rail passing through at least a portion of the etch stop structure, and a backside power rail passing through the substrate, the backside power rail in contact with one end of the via power rail.

公开(公告)号：US20220005763A1

公开(公告)日：2022-01-06

申请号：US17480615

申请日：2021-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jangho LEE ,  Jongmin BAEK ,  Wookyung YOU ,  Kyu-Hee HAN ,  Suhyun BARK

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

Abstract: Disclosed is a semiconductor device comprising a substrate, a first dielectric layer on the substrate, a first lower conductive line in the first dielectric layer, an etch stop layer on the first dielectric layer, a via-structure that penetrates the etch stop layer and connects to the first lower conductive line, a second dielectric layer on the etch stop layer, and an upper conductive line that penetrates the second dielectric layer and connects to the via-structure. The first dielectric layer includes a dielectric pattern at a level higher than a top surface of the first lower conductive line. The upper conductive line is in contact with a top surface of the etch stop layer. The etch stop layer has at an upper portion a rounded surface in contact with the via-structure.

公开(公告)号：US20240234253A1

公开(公告)日：2024-07-11

申请号：US18399173

申请日：2023-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wookyung YOU ,  Yeonggil KIM ,  Sangkoo KANG ,  Minjae KANG ,  Koungmin RYU ,  Hoonseok SEO ,  Woojin LEE

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L24/05 ,  H01L25/0657 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696 ,  H01L2224/0557 ,  H01L2225/06541 ,  H01L2924/13091

Abstract: A semiconductor device includes: a device structure including a first semiconductor substrate and having an active pattern extending in first direction, a conductive through-via electrically connected to a front wiring layer and penetrating through the first semiconductor substrate, wherein the first semiconductor substrate has a non-planarized lower surface in which a peripheral region around the conductive through-via curves downward, a first bonding structure having a planarized insulating layer disposed on the second surface of the first semiconductor substrate and having a planarized upper surface.

公开(公告)号：US20220068810A1

公开(公告)日：2022-03-03

申请号：US17221191

申请日：2021-04-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seonghun LIM ,  Wookyung YOU ,  Kyoungwoo LEE ,  Juyoung JUNG ,  Il Sup KIM ,  Chin KIM ,  Kyoungpil PARK ,  Jinhyung PARK

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/06

Abstract: A semiconductor device including a transistor on a substrate; an interlayer insulating layer on the transistor; a first metal-containing layer on the interlayer insulating layer; and a second metal-containing layer on the first metal-containing layer, wherein the second metal-containing layer includes a resistor, the resistor includes a first insulating layer on the first metal-containing layer; a resistor metal layer on the first insulating layer; and a second insulating layer on the resistor metal layer, and the resistor metal layer includes a recessed side surface.

公开(公告)号：US20240136254A1

公开(公告)日：2024-04-25

申请号：US18320423

申请日：2023-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangkoo KANG ,  Wookyung YOU ,  Minjae KANG ,  Koungmin RYU ,  Hoonseok SEO ,  Woojin LEE ,  Junchae LEE

IPC: H01L23/48 ,  H01L21/762 ,  H01L21/768 ,  H01L27/088

CPC classification number: H01L23/481 ,  H01L21/76224 ,  H01L21/76898 ,  H01L27/088 ,  H01L29/66439

Abstract: An integrated circuit (IC) device includes a substrate, a pair of fin-type active regions protruding from the substrate to define a trench region on the substrate, the fin-type active regions extending in a first lateral direction, a pair of source/drain regions on the fin-type active regions, respectively, a device isolation film in the trench region, the device isolation film apart from the substrate in a vertical direction, an etch stop structure filling at least a portion of the trench region between the substrate and the device isolation film, a via power rail between the pair of fin-type active regions and between the pair of source/drain regions, the via power rail passing through at least a portion of the etch stop structure, and a backside power rail passing through the substrate, the backside power rail in contact with one end of the via power rail.

公开(公告)号：US20230059177A1

公开(公告)日：2023-02-23

申请号：US17720571

申请日：2022-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangshin JANG ,  Wookyung YOU ,  Sangkoo KANG ,  Donghyun ROH ,  Koungmin RYU ,  Jongmin BAEK

IPC: H01L23/528 ,  H01L23/532

Abstract: A semiconductor device including a first conductive layer on a substrate, a second conductive layer on the first conductive layer, a contact structure between the first and second conductive layers, and a barrier structure surrounding a lower region of a side surface of the second conductive layer, wherein the contact structure includes a contact conductive layer having a first upper surface portion and a second upper surface extending from the first upper surface portion and being concave, and a gap-fill pattern fills a space between the second upper surface portion and the second conductive layer and includes a first gap-fill insulating layer including a metal element and a second gap-fill insulating layer including a silicon element, and the barrier structure includes a first etch stop layer and a barrier layer that include same materials as the first insulating material and the second insulating material, respectively, may be provided.