公开(公告)号：US11521902B2

公开(公告)日：2022-12-06

申请号：US17032085

申请日：2020-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sa Hwan Hong ,  Yong Hee Park ,  Kang Ill Seo

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/308

Abstract: Vertical field-effect transistor (VFET) devices and methods of forming the devices are provided. The methods may include forming a channel region including a first channel region and a second channel region, forming a first cavity in the substrate, forming a first bottom source/drain in the first cavity, forming a second cavity in the substrate, and forming a second bottom source/drain in the second cavity. The first cavity may expose a lower surface of the first channel region, and the second cavity may expose a lower surface of the second channel region. The method may also include after forming the first bottom source/drain and the second bottom source/drain, removing a portion of the channel region between the first channel region and the second channel region to separate the first channel region from the second channel region.

公开(公告)号：US20200020599A1

公开(公告)日：2020-01-16

申请号：US16434211

申请日：2019-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sa Hwan Hong ,  Yong Hee Park ,  Kang Ill Seo

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/308

Abstract: Vertical field-effect transistor (VFET) devices and methods of forming the devices are provided. The methods may include forming a channel region including a first channel region and a second channel region, forming a first cavity in the substrate, forming a first bottom source/drain in the first cavity, forming a second cavity in the substrate, and forming a second bottom source/drain in the second cavity. The first cavity may expose a lower surface of the first channel region, and the second cavity may expose a lower surface of the second channel region. The method may also include after forming the first bottom source/drain and the second bottom source/drain, removing a portion of the channel region between the first channel region and the second channel region to separate the first channel region from the second channel region.

公开(公告)号：US10818560B2

公开(公告)日：2020-10-27

申请号：US16434211

申请日：2019-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sa Hwan Hong ,  Yong Hee Park ,  Kang Ill Seo

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/308

Abstract: Vertical field-effect transistor (VFET) devices and methods of forming the devices are provided. The methods may include forming a channel region including a first channel region and a second channel region, forming a first cavity in the substrate, forming a first bottom source/drain in the first cavity, forming a second cavity in the substrate, and forming a second bottom source/drain in the second cavity. The first cavity may expose a lower surface of the first channel region, and the second cavity may expose a lower surface of the second channel region. The method may also include after forming the first bottom source/drain and the second bottom source/drain, removing a portion of the channel region between the first channel region and the second channel region to separate the first channel region from the second channel region.

公开(公告)号：US10665702B2

公开(公告)日：2020-05-26

申请号：US16151511

申请日：2018-10-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil Kang ,  Ill Seo Kang ,  Yong Hee Park ,  Sang Hoon Baek ,  Keon Yong Cheon

IPC: H01L29/66 ,  H01L29/732 ,  H01L27/082 ,  H01L29/06 ,  H01L29/08 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L21/308 ,  H01L29/10 ,  H01L27/06 ,  H01L21/8249 ,  H01L21/8238

Abstract: A vertical bipolar transistor including a substrate including a first well of a first conductivity type and a second well of a second conductivity type different from the first conductivity type, the first well adjoining the second well, a first fin extending, from the first well, a second fin extending from the first well, a third fin extending from the second well, a first conductive region on the first fin, having the second conductivity type and configured to serve as an emitter of the vertical bipolar transistor, a second conductive region on the second fin, having the first conductivity type, and configured to serve as a base of the vertical bipolar transistor, and a third conductive region on the third fin, having the second conductivity type, and configured to serve as a collector of the vertical bipolar transistor may be provided.

公开(公告)号：US10164057B1

公开(公告)日：2018-12-25

申请号：US15878711

申请日：2018-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Yub Jeon ,  Tae Yong Kwon ,  Oh Seong Kwon ,  Soo Yeon Jeong ,  Yong Hee Park ,  Jong Ryeol Yoo

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423

Abstract: A vertical tunnel field effect transistor (VTFET) including a fin structure protruding from a substrate including a source/drain region, an epitaxially-grown source/drain structure on the fin structure, a cap including pillar portions, the pillar portions covering side surfaces of the epitaxially-grown source/drain structure and partially covering side surfaces of a top portion of the fin structure, a gate insulator covering remaining portions of the side surfaces of the fin structure under the pillar portions of the cap, a work function metal gate on the gate insulator, and a separation pattern surrounding a bottom portion of a fin structure such that the work function metal gate is vertically between the cap and the separation pattern, the separation pattern electrically isolating the work function metal gate from the source/drain region, and a method of manufacturing the same may be provided.

公开(公告)号：US10957795B2

公开(公告)日：2021-03-23

申请号：US16845591

申请日：2020-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong Hee Park ,  Myung Gil Kang ,  Young-Seok Song ,  Keon Yong Cheon

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L27/12

Abstract: A vertical field effect transistor (VFET) including a first source/drain region, a channel structure upwardly protruding from the first source/drain region and configured to serve as a channel, the channel structure having a two-dimensional structure in a plan view, the channel structure having an opening at at least one side thereof, the channel structure including one or two first portions and one or more second portions, the one or two first portion extending in a first direction, and the one or more second portions connected to corresponding one or more of the one or more first portions and extending in a second direction, the second direction being different from the first direction, a gate structure horizontally surrounding the channel structure, and a second source/drain region upwardly on the channel structure may be provided.

公开(公告)号：US10892347B2

公开(公告)日：2021-01-12

申请号：US16197752

申请日：2018-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Yub Jeon ,  Tae Yong Kwon ,  Oh Seong Kwon ,  Soo Yeon Jeong ,  Yong Hee Park ,  Jong Ryeol Yoo

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/786 ,  H01L29/739

Abstract: A vertical tunnel field effect transistor (VTFET) including a fin structure protruding from a substrate including a source/drain region, an epitaxially-grown source/drain structure on the fin structure, a cap including pillar portions, the pillar portions covering side surfaces of the epitaxially-grown source/drain structure and partially covering side surfaces of a top portion of the fin structure, a gate insulator covering remaining portions of the side surfaces of the fin structure under the pillar portions of the cap, a work function metal gate on the gate insulator, and a separation pattern surrounding a bottom portion of a fin structure such that the work function metal gate is vertically between the cap and the separation pattern, the separation pattern electrically isolating the work function metal gate from the source/drain region, and a method of manufacturing the same may be provided.

公开(公告)号：US09966446B2

公开(公告)日：2018-05-08

申请号：US15353163

申请日：2016-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong Hee Park ,  Young Seok Song ,  Young Chul Hwang ,  Ui Hui Kwon ,  Keun Ho Lee ,  Jee Soo Chang ,  Jae Hee Choi

IPC: H01L29/76 ,  H01L29/417 ,  H01L29/78 ,  H01L23/532 ,  H01L23/522 ,  H01L29/66

CPC classification number: H01L29/41791 ,  H01L23/5226 ,  H01L23/5329 ,  H01L29/41775 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/7851

Abstract: There is provided a semiconductor device to enhance operating characteristics by reducing parasitic capacitance between a gate electrode and other nodes. The semiconductor device includes: a substrate including an active region, and a field region directly adjacent to the active region; a first fin-type pattern protruding from the substrate in the active region; a first gate electrode disposed on the substrate, intersecting with the first fin-type pattern and including a first portion and a second portion, the first portion intersecting with the first fin-type pattern; a second gate electrode disposed on the substrate, intersecting with the first fin-type pattern and including a third portion and a fourth portion, the fourth portion facing the second portion, and the third portion intersecting with the first fin-type pattern and facing the first portion; a first interlayer insulating structure disposed between the first portion and the third portion, being on the substrate, and having a first dielectric constant; and a second interlayer insulating structure disposed between the second portion and the fourth portion, being on the substrate, and having a second dielectric constant which is different from the first dielectric constant.

公开(公告)号：US10790368B2

公开(公告)日：2020-09-29

申请号：US16275675

申请日：2019-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Chai Jung ,  Myung Gil Kang ,  Kang Ill Seo ,  Seon Bae Kim ,  Yong Hee Park

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/45 ,  H01L29/66 ,  H01L23/522

Abstract: VFET devices are provided. A VFET device includes a substrate including first and second protruding portions. The VFET device includes an isolation region between the first and second protruding portions. The VFET device includes first and second silicide regions on the first and second protruding portions, respectively. Moreover, the VFET device includes a contact on the first and second silicide regions. Related methods of forming a VFET device are also provided.

公开(公告)号：US09905645B2

公开(公告)日：2018-02-27

申请号：US15256136

申请日：2016-09-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung Gil Kang ,  Seung Han Park ,  Yong Hee Park ,  Sang Hoon Baek ,  Sang Woo Lee ,  Keon Yong Cheon ,  Sung Man Whang

IPC: H01L21/336 ,  H01L29/778 ,  H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L29/0847 ,  H01L29/41741 ,  H01L29/41758 ,  H01L29/42376 ,  H01L29/7827 ,  H01L29/7851

Abstract: A vertical field effect transistor is provided as follows. A substrate has a lower drain and a lower source arranged along a first direction in parallel to an upper surface of the substrate. A fin structure is disposed on the substrate and extended vertically from the upper surface of the substrate. The fin structure includes a first end portion and a second end portion arranged along the first direction. A bottom surface of a first end portion of the fin structure and a bottom surface of a second end portion of the fin structure overlap the lower drain and the lower source, respectively. The fin structure includes a sidewall having a lower sidewall region, a center sidewall region and an upper sidewall region. A gate electrode surrounds the center side sidewall region of the fin structure.