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公开(公告)号：US20220328083A1
公开(公告)日：2022-10-13
申请号：US17537937
申请日：2021-11-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seung Pil KO , Yongjae KIM , Geonhee BAE , Gawon LEE , Kilho LEE
Abstract: A magnetic memory device may include a substrate including a first region and a second region, a first interlayer insulating layer on the substrate, a first capping layer on the first interlayer insulating layer, the first capping layer covering the first and second regions of the substrate, a second interlayer insulating layer on a portion of the first capping layer covering the first region of the substrate, a bottom electrode contact included in the second interlayer insulating layer, a magnetic tunnel junction pattern on the bottom electrode contact, and a second capping layer on the second interlayer insulating layer, the second capping layer being in contact with the first capping layer on the second region of the substrate.
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公开(公告)号：US20220255353A1
公开(公告)日：2022-08-11
申请号：US17733607
申请日：2022-04-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongjae KIM , Jaedeok CHA , Seoncheol KIM , Byongjeon LEE , Jungje BAE , Jaesub YOUN
Abstract: An electronic device is provided. The electronic device includes a substrate comprising a touch sensing circuit, which includes a first layer, a second layer overlapping with the first layer, a plurality of first electrode lines arranged on the first layer in a first direction, and a plurality of second electrode lines arranged on the second layer in a second direction that is vertical with respect to the first direction, a coil arranged to at least partially overlap with the substrate, a power transmission circuit for wirelessly transmitting power through the coil, a ground electrically connected to the power transmission circuit, and a control circuit electrically connected to the coil and the ground, wherein the control circuit can be configured to selectively connect the coil to the power transmission circuit or the ground.
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公开(公告)号：US20150272764A1
公开(公告)日：2015-10-01
申请号：US14599804
申请日：2015-01-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongjae KIM , Youn Baek LEE , Jongwon LEE , Byungjune CHOI , Jeonghun KIM , Se-Gon ROH , Minhyung LEE , Hyun Do CHOI , Sunggu KWON , Youngdo KWON
IPC: A61F5/01
CPC classification number: A61F5/0102 , A01D34/90 , A61F2/60 , A61F2/68 , A61F5/01 , A61F5/32 , A61F2005/0141 , A61F2220/0091 , A61H1/02 , A61H1/024 , A61H1/0244 , A61H3/00 , A61H2003/007 , A61H2201/0192 , A61H2201/1207 , A61H2201/163 , A61H2201/1642 , A61H2201/165 , B25J9/00 , Y10T74/20207
Abstract: A frame configured of a plurality of links pivotally connected to one another is flexibly bent, and pins that connect the plurality of links that constitute the frame are inserted into and slide in a curve-shaped slot and a slot in a vertical direction so that, even though the frame is bent, the entire length of the frame is increased and ends of the frame can be moved along a straight line that is horizontal with respect to the ground.
Abstract translation: 由多个可枢转地连接的连杆构成的框架被柔性地弯曲，并且构成框架的多个连杆的连接销被插入到沿垂直方向的曲线形槽和槽中滑动， 即使框架弯曲，框架的整个长度增加，并且框架的端部可以沿着相对于地面水平的直线移动。
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公开(公告)号：US20240213199A1
公开(公告)日：2024-06-27
申请号：US18227646
申请日：2023-07-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungwoo PARK , Yongjae KIM , Heonwoo KIM , Seung-Kwan RYU
IPC: H01L23/00 , H01L23/498 , H01L25/065
CPC classification number: H01L24/13 , H01L23/49816 , H01L24/16 , H01L24/17 , H01L25/0657 , H01L2224/13017 , H01L2224/16225 , H01L2224/1703 , H01L2225/06517 , H01L2225/06544 , H01L2924/37001
Abstract: The present disclosure provides semiconductor packages and methods of fabricating the same. In some embodiments, a semiconductor package includes a substrate including first and second regions, a first pad on the first region, a second pad on the second region, a first dielectric layer on the first region and including a first opening exposing the first pad, a second dielectric layer on the second region and including a second opening exposing the second pad, a first bump structure on the first pad and in the first opening, and a second bump structure on the second pad and in the second opening. A thickness of the first dielectric layer is greater than a thickness of the second dielectric layer. A distance between the substrate and an uppermost end of the first bump structure is longer than a distance between the substrate and an uppermost end of the second bump structure.
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公开(公告)号：US20200206900A1
公开(公告)日：2020-07-02
申请号：US16655831
申请日：2019-10-17
Applicant: Samsung Electronics Co., Ltd. , Korea University of Technology and Education Industry-University Cooperation Foundation
Inventor： Minhyung LEE , Youn Baek LEE , Yongjae KIM , Jongwon LEE , Byungjune CHOI
Abstract: A wearable chair may include a foot frame configured to support a foot of a user; a shank link configured to rotatably connect to the foot frame; a connecting link provided in front of the shank link and configured to rotatably connect to the foot frame; a knee link configured to rotatably connect to each of the shank link and the connecting link; and a thigh link configured to extend from the knee link. The foot frame, the shank link, the connecting link, and the knee link constitute a four-bar linkage.
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Patent Agency Ranking
公开(公告)号：US20200020847A1
公开(公告)日：2020-01-16
申请号：US16286718
申请日：2019-02-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kilho LEE , Gwanhyeob KOH , Yongjae KIM , Yoonjong SONG
Abstract: A magnetic memory device including a substrate including a cell region and a peripheral circuit region; a first interlayer insulating layer covering the cell region and the peripheral circuit region of the substrate; interconnection lines in the first interlayer insulating layer; a peripheral conductive line and a peripheral conductive contact on the first interlayer insulating layer on the peripheral circuit region, the peripheral conductive contact being between the peripheral conductive line and a corresponding one of the interconnection lines; a bottom electrode contact on the first interlayer insulating layer on the cell region and connected to a corresponding one of the interconnection lines; and a data storage pattern on the bottom electrode contact, wherein the peripheral conductive line is at a height between a top surface of the bottom electrode contact and a bottom surface of the bottom electrode contact.
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公开(公告)号：US20150335515A1
公开(公告)日：2015-11-26
申请号：US14692257
申请日：2015-04-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Minhyung LEE , Yongjae KIM , Jeonghun KIM , Youngdo KWON , Se-Gon ROH , Youn Baek LEE , Jongwon LEE , Byungjune CHOI , Hyun Do CHOI
CPC classification number: A61H3/008 , A61F5/0125 , A61H1/024 , A61H1/0244 , A61H3/00 , A61H2201/0192 , A61H2201/1215 , A61H2201/1628 , A61H2201/164 , A61H2201/165 , A61H2201/5007 , A61H2201/5043 , A61H2201/5058 , B25J9/0006
Abstract: A walking assistance apparatus for preventing offset occurring in between a rotating axis of a hip joint of a user and a rotating shaft of the walking assistance apparatus may be provided. The walking assistance apparatus includes a waist fixing apparatus configured to be fixed to a waist of a user, a connecting guide mounted at the waist fixing apparatus and configured to slide in an extension direction of the waist fixing apparatus and rotate on a rotating shaft extending in a vertical direction perpendicular to the extension direction, a rail unit mounted at one side of the connecting guide, the rail unit extending in a vertical direction, and a hip joint configured to slide along the rail unit.
Abstract translation: 可以提供一种用于防止在使用者的髋关节的旋转轴线和步行辅助装置的旋转轴之间发生偏移的行走辅助装置。 步行辅助装置包括：腰部固定装置，其被配置为固定在使用者的腰部;安装在腰部固定装置上的连接导引件，其构造成沿腰部固定装置的延伸方向滑动， 垂直于所述延伸方向的垂直方向，安装在所述连接引导件的一侧的轨道单元，所述轨道单元沿垂直方向延伸;以及髋关节，被配置为沿着所述轨道单元滑动。
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公开(公告)号：US20250079302A1
公开(公告)日：2025-03-06
申请号：US18444990
申请日：2024-02-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byoungjae BAE , Jin-Wook YANG , Seung Pil KO , Yongjae KIM , Junho PARK , Kilho LEE
IPC: H01L23/528 , H01L23/48 , H01L29/417 , H10B61/00
Abstract: A semiconductor device includes a substrate having a top surface and a bottom surface opposite to each other, a gate structure on the top surface of the substrate, a plurality of source/drain patterns on the top surface of the substrate and on opposite sides of the gate structure, a backside conductive line on the bottom surface of the substrate and electrically connected to at least one of the gate structure or a first source/drain pattern of the source/drain patterns, and a magnetic tunnel junction pattern electrically connected to a second source/drain pattern of the source/drain patterns.
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公开(公告)号：US20240324243A1
公开(公告)日：2024-09-26
申请号：US18473660
申请日：2023-09-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongjae KIM , Woojin KIM , Junghoon BAK , Hyunchul SHIN , Hyeonah JO
IPC: H10B61/00 , H01L23/522
CPC classification number: H10B61/22 , H01L23/5226
Abstract: A semiconductor device includes a plurality of data storage patterns on a substrate, the plurality of data storage patterns spaced apart from each other in a first direction parallel to an upper surface of the substrate, a first upper conductive line on the plurality of data storage patterns, extending in the first direction and connected to the plurality of data storage patterns, a second upper conductive line on the first upper conductive line and extending in the first direction and a plurality of via contacts between the first upper conductive line and the second upper conductive line and spaced apart from each other in the first direction. The plurality of via contacts are arranged to be offset from the plurality of data storage patterns in the first direction.
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公开(公告)号：US20240112998A1
公开(公告)日：2024-04-04
申请号：US18461569
申请日：2023-09-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yongjae KIM , Sungwoo PARK , Seungkwan RYU , Yanggyoo JUNG
IPC: H01L23/498 , H01L23/00 , H01L23/31 , H01L23/538
CPC classification number: H01L23/49816 , H01L23/3128 , H01L23/5383 , H01L23/5385 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L2224/13147 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204
Abstract: A semiconductor package includes a package substrate, an interposer mounted on the package substrate via first conductive bumps, first and second semiconductor devices disposed spaced apart from each other on the interposer and mounted on the interposer via second conductive bumps, and an underfill member filling a space between the first conductive bumps that are between the package substrate and the interposer. The interposer includes a central region and a peripheral region at least partially surrounding the central region. The first conductive bumps include first bump structures disposed on second bonding pads, which are in the central region and on a lower surface of the interposer, respectively, and having a circular shape. The first conductive bumps further include second bump structures disposed on second bonding pads, which are in the peripheral region and on the lower surface of the interposer, respectively, and having an elliptical shape.
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