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公开(公告)号：US08760216B2
公开(公告)日：2014-06-24
申请号：US12762456
申请日：2010-04-19
IPC分类号： G05F1/10
摘要： A reference voltage generator circuit may include at least one MOS transistor and at least one bipolar transistor coupled together to provide an electrical path from an input reference potential to an output of the generator circuit. The electrical path may extend through a gate-to-source path of the MOS transistor and further through a base-to-emitter path of the bipolar transistor. The MOS transistor may be biased by a bias current that is proportional to T2·μ(T), where T represents absolute temperature and μ(T) represents mobility of a MOS transistor in the bias current generator. Optionally, the reference voltage generator may include N MOS and M multiple bipolar transistors (N≧1, M≧1), and the output reference voltage may be N*VGS+M*VBE as compared to the input reference potential.
摘要翻译： 参考电压发生器电路可以包括至少一个MOS晶体管和耦合在一起的至少一个双极晶体管，以提供从输入参考电位到发生器电路的输出的电路径。 电路可以延伸穿过MOS晶体管的栅极到源极的路径，并进一步穿过双极晶体管的基极到发射极的路径。 可以通过与T2·μ（T）成比例的偏置电流来偏置MOS晶体管，其中T表示绝对温度，μ（T）表示偏置电流发生器中MOS晶体管的迁移率。 可选地，参考电压发生器可以包括N个MOS和M个多极双极晶体管（N≥1，M≥1），并且与输入的参考电位相比，输出参考电压可以是N * VGS + M * VBE。
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公开(公告)号：US20120249185A1
公开(公告)日：2012-10-04
申请号：US13076814
申请日：2011-03-31
IPC分类号： H03K5/153
CPC分类号： H03K17/0822 , H03K2217/0045
摘要： A detection circuit is coupled to an output terminal of a driver circuit. The detection circuit includes a comparator to compare a signal at the output terminal to a reference signal corresponding to a signal that would be generated if a capacitive load having a relatively high capacitance value were connected to the output terminal. Output of the comparator is sampled at a predetermined time after the driver circuit provides the drive signal. An error signal is generated when the sampled output indicates that the capacitive load having the relatively high capacitance value is actually connected to the output terminal.
摘要翻译： 检测电路耦合到驱动器电路的输出端。 检测电路包括比较器，用于将输出端子处的信号与对应于如果具有相对高的电容值的电容性负载连接到输出端子将产生的信号相比较的参考信号。 在驱动器电路提供驱动信号之后的预定时间对比较器的输出进行采样。 当采样输出指示具有相对较高电容值的电容性负载实际连接到输出端时，产生误差信号。
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公开(公告)号：US08330505B2
公开(公告)日：2012-12-11
申请号：US13076814
申请日：2011-03-31
IPC分类号： H03K3/00
CPC分类号： H03K17/0822 , H03K2217/0045
摘要： A detection circuit is coupled to an output terminal of a driver circuit. The detection circuit includes a comparator to compare a signal at the output terminal to a reference signal corresponding to a signal that would be generated if a capacitive load having a relatively high capacitance value were connected to the output terminal. Output of the comparator is sampled at a predetermined time after the driver circuit provides the drive signal. An error signal is generated when the sampled output indicates that the capacitive load having the relatively high capacitance value is actually connected to the output terminal.
摘要翻译： 检测电路耦合到驱动器电路的输出端。 检测电路包括比较器，用于将输出端子处的信号与对应于如果具有相对高的电容值的电容性负载连接到输出端子将产生的信号相比较的参考信号。 在驱动器电路提供驱动信号之后的预定时间对比较器的输出进行采样。 当采样输出指示具有相对较高电容值的电容性负载实际连接到输出端时，产生误差信号。
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公开(公告)号：US08212617B2
公开(公告)日：2012-07-03
申请号：US12652442
申请日：2010-01-05
IPC分类号： H03F3/18
CPC分类号： H03F3/3023 , H03F2200/91 , H03F2203/30111
摘要： A system for a Class AB Amplifier output stage that includes a first push pull system connected to an output terminal including a first driving transistor coupled to the output terminal and a second push pull system connected to the output terminal including a second driving transistor coupled to the output terminal. The amplifier also includes a current mode amplifier where the current mode amplifier's output is coupled to the first driving transistor's gate. The amplifier further includes a pair of resistors, a first resistor coupled to a first input terminal of the current mode amplifier, a second resistor coupled to a second input terminal of the current mode amplifier and coupled to the second driving transistor.
摘要翻译： 一种用于AB类放大器输出级的系统，包括连接到输出端的第一推挽系统，所述第一推挽系统包括耦合到所述输出端子的第一驱动晶体管和连接到所述输出端子的第二推挽系统，所述第二推挽系统包括耦合到所述输出端 输出端子。 放大器还包括电流模式放大器，其中电流模式放大器的输出耦合到第一驱动晶体管的栅极。 放大器还包括一对电阻器，耦合到电流模式放大器的第一输入端子的第一电阻器，耦合到电流模式放大器的第二输入端子并耦合到第二驱动晶体管的第二电阻器。
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公开(公告)号：US20130050132A1
公开(公告)日：2013-02-28
申请号：US13218788
申请日：2011-08-26
申请人： Javier Calpe Maravilla , Alberto Marinas , Santiago Iriarte , Enrique Company Bosch , Miguel Chanca , Reza Alavi , Vladimir Friedman , John Cleary
发明人： Javier Calpe Maravilla , Alberto Marinas , Santiago Iriarte , Enrique Company Bosch , Miguel Chanca , Reza Alavi , Vladimir Friedman , John Cleary
IPC分类号： G06F3/045
CPC分类号： G06F3/044 , G06F1/3262 , G06F3/0418
摘要： Techniques to control a capacitive touch screen that decrease processing time and increase noise rejection. The techniques may include injecting a plurality of excitation signals having unique spectral profiles onto conductors of the capacitive touch screen, sampling signals returned from the screen, and determining a location of touch. The techniques may further include injecting a plurality of excitation signals having unique spectral profiles onto adjacent or non-adjacent conductors of the capacitive touch screen. The techniques may further include injecting a plurality of excitation signals having unique spectral profiles onto conductors of the capacitive touch screen in unequal measures. The techniques may also include mapping frequency characteristics of noise present on the capacitive touch screen.
摘要翻译： 用于控制电容式触摸屏的技术，其减少处理时间并增加噪声抑制。 这些技术可以包括将具有独特光谱轮廓的多个激励信号注入到电容式触摸屏的导体上，从屏幕返回的采样信号以及确定触摸的位置。 这些技术可以进一步包括将具有唯一光谱轮廓的多个激励信号注入到电容式触摸屏的相邻或非相邻导体上。 这些技术可以进一步包括以不相等的措施将具有独特光谱分布的多个激励信号注入到电容式触摸屏的导体上。 这些技术还可以包括映射存在于电容式触摸屏上的噪声的频率特性。
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公开(公告)号：US08928296B2
公开(公告)日：2015-01-06
申请号：US13112335
申请日：2011-05-20
申请人： Santiago Iriarte , Alberto Marinas
发明人： Santiago Iriarte , Alberto Marinas
摘要： A low dropout voltage regulator (LDO) includes first and second amplifiers and a current mirror. The first amplifier includes a first input receiving a reference voltage and a second input receiving a voltage proportional to an output of the LDO. The current mirror includes an input current at a first end of the current mirror to an output current at a second end of the current mirror, the input current controlled by an output of the first amplifier and the output current being supplied to the output of the LDO. The second amplifier includes a first input coupled to the first end of the current mirror and a second input coupled to the second end of the current mirror.
摘要翻译： 低压差稳压器（LDO）包括第一和第二放大器和电流镜。 第一放大器包括接收参考电压的第一输入端和接收与LDO的输出成正比的电压的第二输入端。 电流镜包括在电流镜的第一端处的输入电流到电流镜的第二端处的输出电流，由第一放大器的输出控制的输入电流和输出电流被提供给电流镜的输出 我愿意。 第二放大器包括耦合到电流镜的第一端的第一输入和耦合到电流镜的第二端的第二输入。
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公开(公告)号：US09098104B2
公开(公告)日：2015-08-04
申请号：US13788917
申请日：2013-03-07
CPC分类号： G05F1/575
摘要： A low drop out voltage regulator comprising: a transistor having an input node, an output node, and a control node; a differential amplifier having an output connected to the control node of the transistor and having a first input node; and a feedback capacitor connected between the output node of the transistor and the first input of the differential amplifier, wherein a voltage at the output of the transistor is dependent on a charge across the feedback capacitor.
摘要翻译： 一种低压降稳压器，包括：具有输入节点，输出节点和控制节点的晶体管; 差分放大器，具有连接到晶体管的控制节点并具有第一输入节点的输出; 以及连接在晶体管的输出节点和差分放大器的第一输入端之间的反馈电容器，其中晶体管的输出端的电压取决于反馈电容器两端的电荷。
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公开(公告)号：US08866499B2
公开(公告)日：2014-10-21
申请号：US12548540
申请日：2009-08-27
申请人： Santiago Iriarte , Mark Murphy
发明人： Santiago Iriarte , Mark Murphy
IPC分类号： G01R27/26
CPC分类号： G01R27/2605
摘要： A system and method for testing capacitance of a load circuit connected to an output pin of a driving circuit In one embodiment, the method may comprise driving a voltage at the output pin to a first voltage; a predetermined current to the output pin; comparing the voltage at the output pin to a reference voltage; and when the voltage at the output pin matches the reference voltage, generating an estimate of capacitance present at the output pin based on a number of clock cycles occurring between an onset of a timed voltage change period and a time at which the voltage at the output pin matches the reference voltage.
摘要翻译： 一种用于测试连接到驱动电路的输出引脚的负载电路的电容的系统和方法。 在一个实施例中，该方法可以包括将输出引脚处的电压驱动到第一电压; 向输出引脚施加预定电流; 将输出引脚上的电压与参考电压进行比较; 并且当输出引脚上的电压与参考电压匹配时，基于在定时电压变化周期的开始与输出端之间的电压的时间之间发生的时钟周期数，产生输出引脚上存在的电容的估计 引脚匹配参考电压。
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公开(公告)号：US20070146061A1
公开(公告)日：2007-06-28
申请号：US11536809
申请日：2006-09-29
申请人： Santiago Iriarte
发明人： Santiago Iriarte
IPC分类号： G05F1/10
CPC分类号： G05F3/262
摘要： A CMOS reference voltage source comprises first and second circuit branches connected in parallel between supply terminals, so that the current in one branch is mirrored in the other, and vice versa. The first circuit branch includes a series connection of a first transistor (MP1) of a first conductivity type, a first transistor (MN1) of a second conductivity type and a second transistor (MN2) of the second conductivity type. The second circuit branch includes a series connection of a second transistor (MP2) of the first conductivity type, a third transistor (MN3) of the second conductivity type and a fourth transistor (MN4) of the second conductivity type. The reference voltage is provided at an interconnection node between the third and fourth transistors (MN3, MN4) of the second conductivity type. No resistors or bipolar devices are needed so that a standard CMOS process can be used.
摘要翻译： CMOS参考电压源包括在供电端子之间并联连接的第一和第二电路分支，使得一个分支中的电流在另一个分支中反映，反之亦然。 第一电路支路包括第一导电类型的第一晶体管（MP 1），第二导电类型的第一晶体管（MN 1）和第二导电类型的第二晶体管（MN 2）的串联连接。 第二电路支路包括第一导电类型的第二晶体管（MP 2），第二导电类型的第三晶体管（MN 3）和第二导电类型的第四晶体管（MN 4）的串联连接。 参考电压设置在第二导电类型的第三和第四晶体管（MN 3，MN 4）之间的互连节点处。 不需要电阻或双极器件，因此可以使用标准CMOS工艺。
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公开(公告)号：US08569861B2
公开(公告)日：2013-10-29
申请号：US12975847
申请日：2010-12-22
申请人： Alan O'Donnell , Santiago Iriarte , Mark J. Murphy , Colin Lyden , Gary Casey , Eoin Edward English
发明人： Alan O'Donnell , Santiago Iriarte , Mark J. Murphy , Colin Lyden , Gary Casey , Eoin Edward English
IPC分类号： H01L29/86 , H01L29/8605
CPC分类号： G01N27/226 , B81B7/00 , B81B7/007 , B81B2201/0214 , G01N27/26 , G01N27/4148 , H01F17/00 , H01F17/04 , H01L21/82 , H01L23/3677 , H01L23/38 , H01L23/473 , H01L23/481 , H01L23/58 , H01L24/05 , H01L24/13 , H01L24/48 , H01L24/94 , H01L25/16 , H01L25/167 , H01L27/0694 , H01L27/14 , H01L27/15 , H01L28/00 , H01L28/10 , H01L28/20 , H01L28/60 , H01L28/82 , H01L28/86 , H01L28/90 , H01L31/0392 , H01L31/0525 , H01L31/0547 , H01L31/056 , H01L31/06 , H01L35/00 , H01L35/28 , H01L35/30 , H01L2224/04042 , H01L2224/05554 , H01L2224/0556 , H01L2224/0557 , H01L2224/32145 , H01L2224/48091 , H01L2224/48265 , H01L2225/06531 , H01L2924/00014 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042 , H01L2924/12043 , H01L2924/14 , H01L2924/1461 , H01L2924/15787 , H01L2924/15788 , H01L2924/16195 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19104 , H02S10/10 , H02S40/38 , Y02E10/50 , Y02E10/52 , H01L2924/00 , H01L2224/45099 , H01L2224/05552 , H01L2224/85399 , H01L2224/05599
摘要： Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.
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