公开(公告)号：US08569861B2

公开(公告)日：2013-10-29

申请号：US12975847

申请日：2010-12-22

申请人： Alan O'Donnell ,  Santiago Iriarte ,  Mark J. Murphy ,  Colin Lyden ,  Gary Casey ,  Eoin Edward English

发明人： Alan O'Donnell ,  Santiago Iriarte ,  Mark J. Murphy ,  Colin Lyden ,  Gary Casey ,  Eoin Edward English

IPC分类号： H01L29/86 ,  H01L29/8605

CPC分类号： G01N27/226 ,  B81B7/00 ,  B81B7/007 ,  B81B2201/0214 ,  G01N27/26 ,  G01N27/4148 ,  H01F17/00 ,  H01F17/04 ,  H01L21/82 ,  H01L23/3677 ,  H01L23/38 ,  H01L23/473 ,  H01L23/481 ,  H01L23/58 ,  H01L24/05 ,  H01L24/13 ,  H01L24/48 ,  H01L24/94 ,  H01L25/16 ,  H01L25/167 ,  H01L27/0694 ,  H01L27/14 ,  H01L27/15 ,  H01L28/00 ,  H01L28/10 ,  H01L28/20 ,  H01L28/60 ,  H01L28/82 ,  H01L28/86 ,  H01L28/90 ,  H01L31/0392 ,  H01L31/0525 ,  H01L31/0547 ,  H01L31/056 ,  H01L31/06 ,  H01L35/00 ,  H01L35/28 ,  H01L35/30 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0556 ,  H01L2224/0557 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48265 ,  H01L2225/06531 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H02S10/10 ,  H02S40/38 ,  Y02E10/50 ,  Y02E10/52 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05552 ,  H01L2224/85399 ,  H01L2224/05599

摘要： Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.

公开(公告)号：US09389275B2

公开(公告)日：2016-07-12

申请号：US13362208

申请日：2012-01-31

申请人： Gabriel Banarie ,  Andreas Callanan ,  Damien McCartney ,  Colin Lyden

发明人： Gabriel Banarie ,  Andreas Callanan ,  Damien McCartney ,  Colin Lyden

IPC分类号： G01R35/00 ,  G01R31/319

CPC分类号： G01R31/3191

摘要： Techniques to provide calibration of a measurement system in conjunction with measurement operations. The techniques may include providing a reference device in a signal processing chain within the measurement system. An excitation signal may be driven through the reference device while it may be connected to the signal processing chain within the measurement system and a calibration response may be captured. During a measurement operation, the reference device connection may be complemented with a sensor connection in the signal processing chain and the excitation signal may be driven through the signal processing chain. A measurement response may be captured from the system. The measurement system may generate a calibrated measurement signal that accounts for phase and/or amplitude errors within the system from the calibration response and the measurement response.

摘要翻译： 与测量操作一起提供测量系统校准的技术。 这些技术可以包括在测量系统内的信号处理链中提供参考装置。 激励信号可以通过参考装置驱动，同时其可以连接到测量系统内的信号处理链，并且可以捕获校准响应。 在测量操作期间，参考设备连接可以与信号处理链中的传感器连接互补，激励信号可以通过信号处理链驱动。 可以从系统捕获测量响应。 测量系统可以产生校准的测量信号，其根据校准响应和测量响应考虑系统内的相位和/或幅度误差。

公开(公告)号：US20110215957A1

公开(公告)日：2011-09-08

申请号：US12717448

申请日：2010-03-04

申请人： Derek HUMMERSTON ,  Christopher Peter Hurrell ,  Colin Lyden

发明人： Derek HUMMERSTON ,  Christopher Peter Hurrell ,  Colin Lyden

IPC分类号： H03M1/12

CPC分类号： H03M1/12

摘要： A pipeline analog to digital converter comprising: a first analog to digital converter for determining a first part of an analog to digital conversion result, and for forming a residue signal; an amplifier for amplifying the residue signal, the amplifier including at least one offset sampling capacitor for sampling an offset of the amplifier, wherein at least one resistance is associated with the at least one capacitor so as to form a filter, and the at least one resistor is variable such that an amplifier bandwidth can be switched between a first bandwidth and a second bandwidth less than the first bandwidth during sampling of the offset.

摘要翻译： 一种管线模数转换器，包括：第一模数转换器，用于确定模数转换结果的第一部分，以及用于形成残留信号; 用于放大残留信号的放大器，所述放大器包括用于对放大器的偏移进行采样的至少一个偏移采样电容器，其中至少一个电阻与所述至少一个电容器相关联以形成滤波器，并且所述至少一个 电阻器是可变的，使得在偏移的采样期间，可以在第一带宽和小于第一带宽的第二带宽之间切换放大器带宽。

公开(公告)号：US20060208935A1

公开(公告)日：2006-09-21

申请号：US11273220

申请日：2005-11-14

申请人： Christopher Hurrell ,  Colin Lyden

发明人： Christopher Hurrell ,  Colin Lyden

IPC分类号： H03M1/12

CPC分类号： H03M1/145 ,  H03M1/144 ,  H03M1/468

摘要： A analog to digital converter, comprising: an input for receiving an input signal to be digitised; a first converter core for performing a first part of an analog to digital conversion, and for outputting a first digital result; a first residue calculator for calculating a first residue as a difference between the input signal and the first digital result; a second converter core for performing a second part of the analog to digital conversion by converting the first residue; wherein at least one of the first and second converter cores comprises at least three analog to digital conversion engines and a controller for controlling the operation of the engines such that the engines collaborate to perform a successive approximation search, and wherein a plurality of bits can be determined during a single trial step of the successive approximation search.

摘要翻译： 一种模数转换器，包括：用于接收要被数字化的输入信号的输入; 用于执行模数转换的第一部分并用于输出第一数字结果的第一转换器核心; 第一残差计算器，用于计算第一残差作为输入信号和第一数字结果之间的差; 第二转换器核，用于通过转换第一残差来执行模数转换的第二部分; 其中所述第一和第二转换器核心中的至少一个包括至少三个模数转换引擎和用于控制引擎的操作的控制器，使得引擎协同执行逐次逼近搜索，并且其中多个位可以是 在逐次逼近搜索的单个试验步骤中确定。

公开(公告)号：US07106234B2

公开(公告)日：2006-09-12

申请号：US11038242

申请日：2005-01-21

申请人： John Oliver O'Connell ,  Colin Lyden

发明人： John Oliver O'Connell ,  Colin Lyden

IPC分类号： H03M1/66

CPC分类号： H03M3/368 ,  H03M3/464

摘要： A DAC (1) has a switched element capacitor (7, Cr) to which charge is delivered via switches (6, S1/S2) depending on required analog voltage level (Vref1, Vref2). An output switch (S3) is closed and a ground switch (S4) is opened to deliver charge to the output according to received bi-level digital inputs (+1, −1). The control block (2) has a memory and determines an inactive output level if there is an input digital transition from +1 to −1 or from −1 to +1. For the inactive level S3 is kept open and S4 is kept closed. Thus, for every clock cycle with one of these transitions there is no charge transfer and hence no thermal noise. Overall noise is therefore considerably reduced.

摘要翻译： DAC（1）具有取决于所需的模拟电压电平（Vref 1，Vref 2）的开关（6，S 1 / S 2）向其输送电荷的开关元件电容器（7，Cr）。 输出开关（S 3）闭合，接地开关（S 4）打开，根据接收到的双电平数字输入（+1，-1）将电荷输送到输出端。 如果存在从+1到-1或从-1到+1的输入数字转换，则控制块（2）具有存储器并且确定不活动的输出电平。 对于无效级别，S 3保持打开，并且S 4保持关闭。 因此，对于具有这些转换之一的每个时钟周期，不存在电荷转移，因此没有热噪声。 因此整体噪音大大降低。

公开(公告)号：US20060164279A1

公开(公告)日：2006-07-27

申请号：US11045672

申请日：2005-01-26

申请人： Robert Brewer ,  Colin Lyden ,  Michael Coln

发明人： Robert Brewer ,  Colin Lyden ,  Michael Coln

IPC分类号： H03M1/12

CPC分类号： G11C27/026 ,  G11C27/024

摘要： An acquisition and averaging circuit is provided in which, during a sampling phase capacitors in sample blocks 4 and 6 are sequentially connected to the input signal to sample it and are then isolated so as to hold the sample. The capacitors are then connected to a combining/averaging arrangement such that an average of the sample values is formed.

公开(公告)号：US20160094240A1

公开(公告)日：2016-03-31

申请号：US14496980

申请日：2014-09-25

申请人： Anthony Evan O'Shaughnessy ,  Colin Lyden ,  Joseph Peter Canning

发明人： Anthony Evan O'Shaughnessy ,  Colin Lyden ,  Joseph Peter Canning

IPC分类号： H03M1/12

CPC分类号： H03M1/1245 ,  H03H17/0621 ,  H03H17/0642 ,  H03H17/0664 ,  H03H17/0685

摘要： It is known to perform sample rate conversion. A sample rate converter is arranged to receive digital data at an input sample rate Fs and to output data at an output sample rate Fo, where Fo=Fs/N, and N is decimation factor greater than 1. A problem can arise with sample rate converters when a user wishes to change the decimation rate. Generally a sample rate converter needs to discard the samples in its filter when the decimation rate is changed, and the filter output is unusable until the filter has refilled with values taken at the new decimation rate. The sample rate converter provided here does not suffer from this problem. The sample rate converter includes at least Q channels. Each channel comprises a Qth order filter arranged to select input signals at predetermined intervals from a run of P input signals, and to form a weighted sum of the selected input signals to generate an output value, and where the runs of P input signals of one channel are offset from the runs of P signals of the other channels.

摘要翻译： 已知进行采样率转换。 采样率转换器被布置为以输入采样率Fs接收数字数据，并以输出采样率Fo输出数据，其中Fo = Fs / N，N是抽取因子大于1.可能会出现采样率的问题 转换器，当用户希望改变抽取率时。 通常，抽样速率改变时，采样率转换器需要丢弃其滤波器中的样本，并且滤波器输出不可用，直到滤波器用新的抽取率取值为止。 这里提供的采样率转换器不会受到这个问题的困扰。 采样率转换器至少包括Q个通道。 每个通道包括Q阶滤波器，其布置成从P个输入信号的行程中以预定间隔选择输入信号，并且形成所选输入信号的加权和以产生输出值，并且其中一个P输入信号的运行 通道偏离其他通道的P信号的运行。

公开(公告)号：US08659349B1

公开(公告)日：2014-02-25

申请号：US13626630

申请日：2012-09-25

申请人： Colin Lyden ,  Donal Bourke ,  Dennis A. Dempsey ,  Dermot G. O'Keeffe ,  Patrick Kirby

发明人： Colin Lyden ,  Donal Bourke ,  Dennis A. Dempsey ,  Dermot G. O'Keeffe ,  Patrick Kirby

IPC分类号： G06G7/12

CPC分类号： G01N27/028 ,  G01N27/3273 ,  G01N27/49 ,  H03F1/34 ,  H03F3/45475 ,  H03F2200/261 ,  H03F2200/462 ,  H03L5/00

摘要： A control circuit for use with a four terminal sensor, the sensor having first and second drive terminals and first and second measurement terminals, the control circuit arranged to drive at least one of the first and second drive terminals with an excitation signal, to sense a voltage difference between the first and second measurement terminals, and control the excitation signal such that the voltage difference between the first and second measurement terminals is within a target range of voltages, and wherein the control circuit includes N poles in its transfer characteristic and N−1 zeros in its transfer characteristic such that when a loop gain falls to unity the phase shift around a closed loop is not substantially 2π radians or a multiple thereof, where N is greater than 1.

摘要翻译： 一种与四端子传感器一起使用的控制电路，所述传感器具有第一和第二驱动端子以及第一和第二测量端子，所述控制电路被布置成用激励信号驱动第一和第二驱动端子中的至少一个，以感测 并且控制所述激励信号，使得所述第一测量端子与所述第二测量端子之间的电压差在目标电压范围内，并且其中所述控制电路在其传输特性中包括N极，并且所述N- 1的零传递特性使得当环路增益下降到1时，围绕闭环的相移基本上不是2pi弧度或其倍数，其中N大于1。

公开(公告)号：US08040264B2

公开(公告)日：2011-10-18

申请号：US12717448

申请日：2010-03-04

申请人： Derek Hummerston ,  Christopher Peter Hurrell ,  Colin Lyden

发明人： Derek Hummerston ,  Christopher Peter Hurrell ,  Colin Lyden

IPC分类号： H03M1/06

CPC分类号： H03M1/12

摘要： A pipeline analog to digital converter comprising: a first analog to digital converter for determining a first part of an analog to digital conversion result, and for forming a residue signal; an amplifier for amplifying the residue signal, the amplifier including at least one offset sampling capacitor for sampling an offset of the amplifier, wherein at least one resistance is associated with the at least one capacitor so as to form a filter, and the at least one resistor is variable such that an amplifier bandwidth can be switched between a first bandwidth and a second bandwidth less than the first bandwidth during sampling of the offset.

摘要翻译： 一种管线模数转换器，包括：第一模数转换器，用于确定模数转换结果的第一部分，以及用于形成残留信号; 用于放大残留信号的放大器，所述放大器包括用于对放大器的偏移进行采样的至少一个偏移采样电容器，其中至少一个电阻与所述至少一个电容器相关联以形成滤波器，并且所述至少一个 电阻器是可变的，使得在偏移的采样期间，可以在第一带宽和小于第一带宽的第二带宽之间切换放大器带宽。

公开(公告)号：US20090140897A1

公开(公告)日：2009-06-04

申请号：US11998618

申请日：2007-11-30

申请人： John Healy ,  Colin Lyden

发明人： John Healy ,  Colin Lyden

IPC分类号： H03M1/06

CPC分类号： H03M3/484 ,  H03M3/338 ,  H03M3/434

摘要： A gain matching method for a single bit gain ranging analog to digital converter including selecting, in response to a gain setting, a number of gain elements to be enabled in a multi-element gain controlled array interconnected between an analog input and an analog to digital converter, and patterning the enablement of the selected number of gain elements among the gain elements for matching the gain of the analog to digital converter for a range of gain settings of the converter to reduce in-band gain error due to gain element mismatch.

摘要翻译： 一种用于单位增益测距模数转换器的增益匹配方法，包括响应于增益设置，选择在模拟输入和模数转换器之间互连的多元件增益控制阵列中使能的增益元件数量 转换器，并且在增益元件中对选定数量的增益元件的启用进行构图，以便在转换器的增益设置的范围内匹配模数转换器的增益，以减少由于增益元件失配引起的带内增益误差。