摘要:
A technique includes sharing common external terminals of a memory device to communicate data and an address with the memory device for a given memory operation. Different sets of address bits indicative of the address are communicated over the common external terminals at different times.
摘要:
System, apparatus, and method to enable and disable a mode of operation of a stacked circuit arrangement on an independent circuit basis using register bits and a single shared mode control line.
摘要:
A memory controller includes a memory to store results of a reference performance test (RT) performed on a non-volatile memory (NVM) die, where the results of the RT include one or more first indicators of failure associated with one or more first read/write cycles of the NVM die before the NVM die is placed in use. The memory controller further includes an analyzer coupled with the memory to perform, in one or more second read/write cycles, one or more field tests that provide second indicators of failure associated with one or more second read/write cycles of the NVM die during the use of the NVM die, and further to predict and dynamically adjust, over one or more second read/write cycles, at least one of likelihood or expected time of failure of the NVM, based at least in part on the first and second indicators of failure.
摘要:
A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.
摘要:
Embodiments of a method, device, and system for implementing multi-level memory with direct access are disclosed. In one embodiment, the method includes designating an amount of a non-volatile random access memory (NVRAM) in a computer system to be utilized as a memory alternative for a dynamic random access memory (DRAM). The method continues by designating a second amount of the NVRAM to be utilized as a storage alternative for a mass storage device. Then the method re-designates at least a first portion of the first amount of NVRAM from the memory alternative designation to the storage alternative designation during operation of the computer system. Finally, the method re-designates at least a first portion of the second amount of NVRAM from the storage alternative designation to the memory alternative designation during operation of the computer system.
摘要:
Examples are disclosed for adaptive configuration of non-volatile memory. The examples include a mode register configured to include default and updated values to indicate one or more configurations of the non-volatile memory. The examples may also include discoverable capabilities maintained in a configuration table that may indicate memory address lengths and/or operating power states.
摘要:
Some embodiments of the invention pertain to a memory system containing multiple memory devices, in which one or multiple ones of the memory devices may flexibly be selected at one time for a common operation to be performed by all the selected devices concurrently.
摘要:
A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.
摘要:
Examples are disclosed for adaptive configuration of non-volatile memory. The examples include a mode register configured to include default and updated values to indicate one or more configurations of the non-volatile memory. The examples may also include discoverable capabilities maintained in a configuration table that may indicate memory address lengths and/or operating power states.
摘要:
A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.