公开(公告)号：US11735435B2

公开(公告)日：2023-08-22

申请号：US16853186

申请日：2020-04-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dan Okamoto ,  Hiroyuki Sada

IPC: H01L21/56 ,  H01L23/498 ,  H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L21/561 ,  H01L23/3157 ,  H01L23/49541 ,  H01L23/49805 ,  H01L23/49861 ,  H01L24/97 ,  H01L23/3107 ,  H01L23/5389 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A quad flat no lead (“QFN”) package that includes a die having an active side positioned substantially in a first plane and a backside positioned substantially in a second plane parallel to the first plane; a plurality of separate conductive pads each having a first side positioned substantially in the first plane and a second side positioned substantially in the second plane; and mold compound positioned between the first and second planes in voids between the conductive pads and the dies. Also a method of producing a plurality of QFN packages includes forming a strip of plastic material having embedded therein a plurality of dies and a plurality of conductive pads that are wire bonded to the dies and singulating the strip into a plurality of QFN packages by cutting through only the plastic material.

公开(公告)号：US20170352609A1

公开(公告)日：2017-12-07

申请号：US15684620

申请日：2017-08-23

Applicant: Texas Instruments Incorporated

Inventor： Dan Okamoto

IPC: H01L23/495 ,  H01L21/78 ,  H01L21/48

CPC classification number: H01L23/49513 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/78 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49582 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00014

Abstract: A leadframe wherein the outer sidewalls of the leadframe that are exposed by sawing during singulation are comprised of greater than 50% solder. A leadframe strip wherein the saw streets and the outer surface of the lead frames are comprised of greater than 50% solder. A method of forming a leadframe strip wherein the saw streets and the outer surface of the lead frames are comprised primarily of solder. A method of forming a leadframe strip wherein the saw streets and the outer surface of the lead frames are comprised entirely of solder.

公开(公告)号：US20150364373A1

公开(公告)日：2015-12-17

申请号：US14301942

申请日：2014-06-11

Applicant: Texas Instruments Incorporated

Inventor： Dan Okamoto ,  Hiroyuki Sada

IPC: H01L21/78 ,  H01L23/28 ,  H01L21/56 ,  H01L23/495

Abstract: A quad flat no lead (“QFN”) package that includes a die having an active side positioned substantially in a first plane and a backside positioned substantially in a second plane parallel to the first plane; a plurality of separate conductive pads each having a first side positioned substantially in the first plane and a second side positioned substantially in the second plane; and mold compound positioned between the first and second planes in voids between the conductive pads and the dies. Also a method of producing a plurality of QFN packages includes forming a strip of plastic material having embedded therein a plurality of dies and a plurality of conductive pads that are wire bonded to the dies and singulating the strip into a plurality of QFN packages by cutting through only the plastic material.

Abstract translation: 一种四边形扁平无铅（“QFN”）封装，其包括具有基本上位于第一平面中的有源侧的管芯和基本上位于平行于第一平面的第二平面中的背面; 多个单独的导电焊盘，其各自具有基本位于所述第一平面中的第一侧和基本位于所述第二平面中的第二侧; 以及位于导电垫和模具之间的空隙中的第一和第二平面之间的模具复合体。 另外，制造多个QFN封装的方法包括：形成嵌入有多个管芯的塑料材料条和多个导线焊盘，所述多个导体焊盘被引线接合到管芯上，并通过切割将所述条带分割成多个QFN封装 只有塑料材质。

公开(公告)号：US20160133599A1

公开(公告)日：2016-05-12

申请号：US14535939

申请日：2014-11-07

Applicant: Texas Instruments Incorporated

Inventor： Dan Okamoto

IPC: H01L23/00 ,  H01L23/31 ,  G03F7/20 ,  H01L23/495

CPC classification number: H01L23/49805 ,  H01L21/4821 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/4839 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3185 ,  H01L23/495 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/96 ,  H01L2221/68372 ,  H01L2221/68386 ,  H01L2224/48175 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/1816 ,  H01L2924/18165 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A method of making a flat no lead package including attaching a first plurality of leads in spaced apart relationship in a predetermined pattern on a tape and attaching a first die to the tape at a predetermined position within the predetermined lead pattern.

Abstract translation: 一种制造扁平的无引线封装的方法，包括以预定图案以带间隔的关系附接第一多个引线并将第一裸片附接到预定引线图案中的预定位置处的带上。

公开(公告)号：US20150348881A1

公开(公告)日：2015-12-03

申请号：US14290153

申请日：2014-05-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dan Okamoto

IPC: H01L23/495 ,  B23K35/02 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48

CPC classification number: B23K35/025 ,  H01L21/4825 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/83 ,  H01L2224/2732 ,  H01L2224/2741 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/35821 ,  H01L2224/35823 ,  H01L2224/37147 ,  H01L2224/3756 ,  H01L2224/376 ,  H01L2224/40105 ,  H01L2224/40145 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method of making a QFD package including providing a clip and coating at least a first end portion of the clip with solder paste.

Abstract translation: 一种制造QFD封装的方法，包括提供夹子并用焊膏涂覆夹子的至少第一端部分。

公开(公告)号：US20200251352A1

公开(公告)日：2020-08-06

申请号：US16853186

申请日：2020-04-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dan Okamoto ,  Hiroyuki Sada

IPC: H01L21/56 ,  H01L23/495 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31

Abstract: A quad flat no lead (“QFN”) package that includes a die having an active side positioned substantially in a first plane and a backside positioned substantially in a second plane parallel to the first plane; a plurality of separate conductive pads each having a first side positioned substantially in the first plane and a second side positioned substantially in the second plane; and mold compound positioned between the first and second planes in voids between the conductive pads and the dies. Also a method of producing a plurality of QFN packages includes forming a strip of plastic material having embedded therein a plurality of dies and a plurality of conductive pads that are wire bonded to the dies and singulating the strip into a plurality of QFN packages by cutting through only the plastic material.

公开(公告)号：US20170271244A1

公开(公告)日：2017-09-21

申请号：US15075298

申请日：2016-03-21

Applicant: Texas Instruments Incorporated

Inventor： Dan Okamoto

IPC: H01L23/495 ,  H01L21/78 ,  H01L21/48

CPC classification number: H01L23/49513 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/78 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49582 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00014

Abstract: A leadframe wherein the outer sidewalls of the leadframe that are exposed by sawing during singulation are comprised of greater than 50% solder. A leadframe strip wherein the saw streets and the outer surface of the lead frames are comprised of greater than 50% solder. A method of forming a leadframe strip wherein the saw streets and the outer surface of the lead frames are comprised primarily of solder. A method of forming a leadframe strip wherein the saw streets and the outer surface of the lead frames are comprised entirely of solder.

公开(公告)号：US10665475B2

公开(公告)日：2020-05-26

申请号：US14301942

申请日：2014-06-11

Applicant: Texas Instruments Incorporated

Inventor： Dan Okamoto ,  Hiroyuki Sada

IPC: H01L21/56 ,  H01L23/495 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L23/538

Abstract: A quad flat no lead (“QFN”) package that includes a die having an active side positioned substantially in a first plane and a backside positioned substantially in a second plane parallel to the first plane; a plurality of separate conductive pads each having a first side positioned substantially in the first plane and a second side positioned substantially in the second plane; and mold compound positioned between the first and second planes in voids between the conductive pads and the dies. Also a method of producing a plurality of QFN packages includes forming a strip of plastic material having embedded therein a plurality of dies and a plurality of conductive pads that are wire bonded to the dies and singulating the strip into a plurality of QFN packages by cutting through only the plastic material.

公开(公告)号：US09536753B2

公开(公告)日：2017-01-03

申请号：US14504971

申请日：2014-10-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yohei Koto ,  Kazunori Hayata ,  Dan Okamoto

IPC: H01L23/48 ,  H01L23/34 ,  H01L23/04 ,  H01L23/52 ,  H01L21/311 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L21/268 ,  H01L23/495 ,  H01L23/00

CPC classification number: H01L21/31111 ,  H01L21/268 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/49517 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/24 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/04 ,  H01L2224/04042 ,  H01L2224/24226 ,  H01L2224/245 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/82104 ,  H01L2224/92164 ,  H01L2224/92244 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/386 ,  H01L2224/85 ,  H01L2224/82 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2224/18 ,  H01L2224/45099 ,  H01L2924/20751

Abstract: A packaged integrated circuit (IC) includes a substrate including a first substrate pad disposed on a first side of the substrate, an IC die disposed on the first side of the substrate, and a first insulating layer molded over the IC die and the substrate. The IC die includes a first die pad on a side of the die opposite from a side of the die adjacent to the first side of the substrate. The first insulating layer includes a first channel extending through the first insulating layer to the first substrate pad, a second channel extending through the first insulating layer to the first die pad, conductive paste filling the first channel and in contact with the first substrate pad, and conductive paste filling the second channel and in contact with the die pad.

Abstract translation: 封装集成电路（IC）包括：衬底，其包括设置在衬底的第一侧上的第一衬底焊盘;设置在衬底的第一侧上的IC管芯;以及模制在IC管芯和衬底上的第一绝缘层。 IC管芯包括在模具的与衬底的第一侧相邻的模具侧面上的第一裸片焊盘。 第一绝缘层包括延伸穿过第一绝缘层到第一衬底焊盘的第一沟道，延伸穿过第一绝缘层到第一裸片焊盘的第二沟道，填充第一沟道并与第一衬底焊盘接触的导电膏， 以及填充第二通道并与管芯焊盘接触的导电膏。

公开(公告)号：US20160315036A1

公开(公告)日：2016-10-27

申请号：US14695333

申请日：2015-04-24

Applicant: Texas Instruments Incorporated

Inventor： Makoto Shibuya ,  Dan Okamoto

IPC: H01L23/495 ,  H01L25/00 ,  H01L29/66 ,  H01L25/07 ,  H01L29/45 ,  H01L29/78

CPC classification number: H01L23/49562 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/38 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/38 ,  H01L2224/40245

Abstract: A dual transistor device includes a first transistor having a first drain, a first gate, and first source and a second transistor having a second drain, a second gate, and a second source. A first terminal is substantially flat and has a first surface. The first source is located adjacent a first portion of the first surface and is electrically coupled to the first terminal. The second drain is located adjacent a second portion of the first surface and is electrically coupled to the first terminal.

Abstract translation: 双晶体管器件包括具有第一漏极，第一栅极和第一源极的第一晶体管和具有第二漏极，第二栅极和第二源极的第二晶体管。 第一端子基本上平坦并具有第一表面。 第一源极位于第一表面的第一部分附近并且电耦合到第一端子。 第二漏极位于第一表面的第二部分附近并且电耦合到第一端子。