摘要:
A semiconductor package is disclosed. The semiconductor package includes an electrically conducting carrier having a mounting surface, a first level first semiconductor power device having a first load electrode mounted over the mounting surface of the electrically conducting carrier and having a second load electrode opposite the first electrode. The package further includes a first level second semiconductor power device. A first connection element has a first surface connected to the second load electrode of the first level first semiconductor power device. A second connection element has a first surface connected to the second load electrode of the first level second semiconductor power device. The package includes a second level first semiconductor power device and a second level second semiconductor power device.
摘要:
A method includes providing a semiconductor chip having a first main surface and a second main surface. A semiconductor chip is placed on a carrier with the first main surface of the semiconductor chip facing the carrier. A first layer of solder material is provided between the first main surface and the carrier. A contact clip including a first contact area is placed on the semiconductor chip with the first contact area facing the second main surface of the semiconductor chip. A second layer of solder material is provided between the first contact area and the second main surface. Thereafter, heat is applied to the first and second layers of solder material to form diffusion solder bonds between the carrier, the semiconductor chip and the contact clip.
摘要:
The present invention intends to provide a power semiconductor device using a high-temperature lead-free solder material, the high-temperature lead-free solder material having the heat resistant property at 280° C. or more, and the bondability at 400° C. or less, and excellent in the suppliabilty and wettability of solder, and in the high-temperature storage reliability and the temperature cycle reliability. In the power semiconductor device according to the present invention, a semiconductor element and a metal electrode member were bonded each other by a high-temperature solder material comprising Sn, Sb, Ag, and Cu as the main constitutive elements and the rest of other unavoidable impurity elements wherein the high-temperature solder material comprises 42 wt %≦Sb/(Sn+Sb)≦48 wt %, 5 wt %≦Ag
摘要:
A method includes providing a semiconductor chip having a first main surface and a second main surface. A semiconductor chip is placed on a carrier with the first main surface of the semiconductor chip facing the carrier. A first layer of solder material is provided between the first main surface and the carrier. A contact clip including a first contact area is placed on the semiconductor chip with the first contact area facing the second main surface of the semiconductor chip. A second layer of solder material is provided between the first contact area and the second main surface. Thereafter, heat is applied to the first and second layers of solder material to form diffusion solder bonds between the carrier, the semiconductor chip and the contact clip.
摘要:
In one embodiment, a leadframe for a semiconductor package includes a source connection area for one transistor and a drain connection point for a second transistor, and a common connection for using a connection clip to couple a drain of the first transistor to a source of the second transistor and to the common connection.
摘要:
The present invention intends to provide a power semiconductor device using a high-temperature lead-free solder material, the high-temperature lead-free solder material having the heat resistant property at 280° C. or more, and the bondability at 400° C. or less, and excellent in the suppliabilty and wettability of solder, and in the high-temperature storage reliability and the temperature cycle reliability. In the power semiconductor device according to the present invention, a semiconductor element and a metal electrode member were bonded each other by a high-temperature solder material comprising Sn, Sb, Ag, and Cu as the main constitutive elements and the rest of other unavoidable impurity elements wherein the high-temperature solder material comprises 42 wt %≦Sb/(Sn+Sb)≦48 wt %, 5 wt %≦Ag
摘要翻译:本发明旨在提供一种使用高温无铅焊料的功率半导体器件,具有280℃以上的耐热性的高温无铅焊料以及400℃下的结合性 或更低,焊料的可供应性和润湿性优异,以及高温存储的可靠性和温度循环的可靠性。 在根据本发明的功率半导体器件中,半导体元件和金属电极构件通过包含Sn,Sb,Ag和Cu的高温焊料作为主要构成元素彼此接合,其余的不可避免的 杂质元素,其中高温焊料材料包含42重量%<= Sb /(Sn + Sb)<= 48重量%,5重量%<= Ag <20重量%,3重量%<= Cu <10重量% 和Ag + Cu <= 25wt%。
摘要:
A power conversion device including a low-side MOSFET, a high-side MOSFET and an integrated control IC chip is disclosed. The power conversion device further includes a substrate comprising a first mounting area having a first group of welding discs and a second mounting area having a second group of welding discs; a first chip flipped and attached to the first mounting area; a second chip flipped and attached to the second mounting area; a metal clip; and a molding body covering a front surface of the substrate, the first chip, the second chip and the metal clip. Metal pads on a front side of the first chip is attached to the first group of welding discs. Metal pads on a front side of the second chip is attached to the second group of welding discs. The metal clip connects a connection pad to a back metal layer of the first chip.
摘要:
The long sides of a rectangular control chip and the long sides of a rectangular memory chip are arranged parallel with first sides of the upper surface of a wiring substrate in a BGA. A lid includes a pair of first brims and a pair of second brims, the widths of the second brims are formed wider than those of the first brims, and a mounting area for mounting chip parts and a junction base area for joining the lid are secured outside the short sides of the control chip mounted on the upper surface of the wiring substrate and outside the short sides of the memory chip mounted on the upper surface of the wiring substrate, which enables the wide-width second brims of the lid to be disposed on the junction base area. Hence, the mounting area of the BGA can be reduced.
摘要:
In one embodiment, a leadframe for a semiconductor package includes a source connection area for one transistor and a drain connection point for a second transistor, and a common connection for using a connection clip to couple a drain of the first transistor to a source of the second transistor and to the common connection.