公开(公告)号：US20110147754A1

公开(公告)日：2011-06-23

申请号：US12970460

申请日：2010-12-16

申请人： Toshiyuki ISA ,  Atsushi HIROSE

发明人： Toshiyuki ISA ,  Atsushi HIROSE

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/78696 ,  H01L27/12 ,  H01L27/124 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/78678

摘要： Disclosed is a thin film transistor including: a gate insulating layer covering a gate electrode; a microcrystalline semiconductor region over the gate insulating layer; a pair of amorphous semiconductor region over the microcrystalline semiconductor; a pair of impurity semiconductor layers over the amorphous semiconductor regions; and wirings over the impurity semiconductor layers. The microcrystalline semiconductor region has a surface having a projection and depression on the gate insulating layer side. The microcrystalline semiconductor region includes a first microcrystalline semiconductor region which is not covered with the amorphous regions and a second microcrystalline semiconductor region which is in contact with the amorphous semiconductor regions. A thickness d1 of the first microcrystalline semiconductor region is smaller than a thickness d2 of the second microcrystalline semiconductor region and d1 is greater than or equal to 30 nm.

摘要翻译： 公开了一种薄膜晶体管，包括：覆盖栅电极的栅极绝缘层; 栅极绝缘层上的微晶半导体区域; 微晶半导体上的一对非晶半导体区域; 在所述非晶半导体区域上的一对杂质半导体层; 以及杂质半导体层上的布线。 微晶半导体区域具有在栅极绝缘层侧具有突出和凹陷的表面。 微晶半导体区域包括未被无定形区域覆盖的第一微晶半导体区域和与非晶半导体区域接触的第二微晶半导体区域。 第一微晶半导体区域的厚度d1小于第二微晶半导体区域的厚度d2，d1大于或等于30nm。

公开(公告)号：US20100148175A1

公开(公告)日：2010-06-17

申请号：US12633067

申请日：2009-12-08

申请人： Hiromichi GODO ,  Satoshi KOBAYASHI ,  Hidekazu MIYAIRI ,  Toshiyuki ISA ,  Shunpei YAMAZAKI

发明人： Hiromichi GODO ,  Satoshi KOBAYASHI ,  Hidekazu MIYAIRI ,  Toshiyuki ISA ,  Shunpei YAMAZAKI

IPC分类号： H01L29/786

CPC分类号： H01L29/78696 ,  H01L27/12 ,  H01L29/04

摘要： Off current of a bottom gate thin film transistor in which a semiconductor layer is shielded from light by a gate electrode is reduced. A thin film transistor includes a gate electrode layer; a first semiconductor layer; a second semiconductor layer, provided on and in contact with the first semiconductor layer; a gate insulating layer between and in contact with the gate electrode layer and the first semiconductor layer; impurity semiconductor layers in contact with the second semiconductor layer; and source and drain electrode layers partially in contact with the impurity semiconductor layers and the first and second semiconductor layers. The entire surface of the first semiconductor layer on the gate electrode layer side is covered by the gate electrode layer; and a potential barrier at a portion where the first semiconductor layer is in contact with the source or drain electrode layer is 0.5 eV or more.

摘要翻译： 其中半导体层被栅极电极遮挡光的底栅薄膜晶体管的截止电流减小。 薄膜晶体管包括栅电极层; 第一半导体层; 第二半导体层，设置在第一半导体层上并与第一半导体层接触; 在栅极电极层和第一半导体层之间并与之接触的栅极绝缘层; 与第二半导体层接触的杂质半导体层; 以及与杂质半导体层和第一和第二半导体层部分接触的源极和漏极电极层。 栅极电极层侧的第一半导体层的整个表面被栅电极层覆盖; 并且在第一半导体层与源极或漏极电极层接触的部分处的势垒为0.5eV以上。

公开(公告)号：US20090321737A1

公开(公告)日：2009-12-31

申请号：US12490447

申请日：2009-06-24

申请人： Toshiyuki ISA ,  Yasuhiro JINBO ,  Sachiaki TEZUKA ,  Koji DAIRIKI ,  Hidekazu MIYAIRI ,  Shunpei YAMAZAKI ,  Takuya HIROHASHI

发明人： Toshiyuki ISA ,  Yasuhiro JINBO ,  Sachiaki TEZUKA ,  Koji DAIRIKI ,  Hidekazu MIYAIRI ,  Shunpei YAMAZAKI ,  Takuya HIROHASHI

IPC分类号： H01L29/04

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78696

摘要： A thin film transistor includes, as a buffer layer, a semiconductor layer which contains nitrogen and includes crystal regions in an amorphous structure between a gate insulating layer and source and drain regions, at least on the source and drain regions side. As compared to a thin film transistor in which an amorphous semiconductor is included in a channel formation region, on-current of a thin film transistor can be increased. In addition, as compared to a thin film transistor in which a microcrystalline semiconductor is included in a channel formation region, off-current of a thin film transistor can be reduced.

摘要翻译： 至少在源区和漏区侧，薄膜晶体管包括作为缓冲层的半导体层，该半导体层含有氮并且包括在栅极绝缘层和源极和漏极区之间的非晶结构中的晶体区域。 与在沟道形成区域中包含非晶半导体的薄膜晶体管相比，可以提高薄膜晶体管的导通电流。 此外，与在沟道形成区域中包含微晶半导体的薄膜晶体管相比，可以减小薄膜晶体管的截止电流。

公开(公告)号：US20090261328A1

公开(公告)日：2009-10-22

申请号：US12423123

申请日：2009-04-14

申请人： Hidekazu MIYAIRI ,  Koji DAIRIKI ,  Yuji EGI ,  Yasuhiro JINBO ,  Toshiyuki ISA

发明人： Hidekazu MIYAIRI ,  Koji DAIRIKI ,  Yuji EGI ,  Yasuhiro JINBO ,  Toshiyuki ISA

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L27/1288 ,  C23C16/0272 ,  C23C16/24 ,  C23C16/4404 ,  H01L27/1214 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/66765 ,  H01L29/78621 ,  H01L29/78669 ,  H01L29/78678 ,  H01L29/78696

摘要： Disclosed is a thin film transistor which includes, over a substrate having an insulating surface, a gate insulating layer covering a gate electrode; a semiconductor layer which functions as a channel formation region; and a semiconductor layer including an impurity element imparting one conductivity type. The semiconductor layer exists in a state that a plurality of crystalline particles is dispersed in an amorphous silicon and that the crystalline particles have an inverted conical or inverted pyramidal shape. The crystalline particles grow approximately radially in a direction in which the semiconductor layer is deposited. Vertexes of the inverted conical or inverted pyramidal crystal particles are located apart from an interface between the gate insulating layer and the semiconductor layer.

摘要翻译： 公开了一种薄膜晶体管，其在具有绝缘表面的衬底上方包括覆盖栅电极的栅绝缘层; 用作沟道形成区域的半导体层; 以及包含赋予一种导电型的杂质元素的半导体层。 半导体层以多个结晶粒子分散在非晶硅中的状态存在，并且结晶粒子具有倒锥形或倒棱锥形状。 晶体颗粒沿半导体层沉积的方向大致径向生长。 倒锥形或倒锥形晶体颗粒的顶点位于与栅极绝缘层和半导体层之间的界面之外。

公开(公告)号：US20110165741A1

公开(公告)日：2011-07-07

申请号：US13050117

申请日：2011-03-17

申请人： Shunpei YAMAZAKI ,  Osamu NAKAMURA ,  Shinji MAEKAWA ,  Gen FUJII ,  Toshiyuki ISA

发明人： Shunpei YAMAZAKI ,  Osamu NAKAMURA ,  Shinji MAEKAWA ,  Gen FUJII ,  Toshiyuki ISA

IPC分类号： H01L21/336

CPC分类号： H01L51/0022 ,  G09G3/3208 ,  G09G3/3225 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/0251 ,  H01L27/1285 ,  H01L27/1292 ,  H01L27/3244 ,  H01L51/055 ,  H01L51/529

摘要： The invention provides a display device and a method for manufacturing thereof by increasing a material efficiently as well as simplifying steps. Also, the invention provides a technique for forming a pattern such as a wiring, that is used for forming a display device, to have a predetermined shape with an excellent controllability. The method for manufacturing a display device includes the steps of: forming a lyophobic region; selectively irradiating laser beam in the lyophobic region to form a lyophilic region; selectively discharging a composition, that contains a conductive material, in the lyophilic region to form a gate electrode layer; forming a gate insulating layer and a semiconductor layer over the gate electrode layer; discharging a composition containing a conductive material over the semiconductor layer to form a source electrode layer and a drain electrode layer; and forming a pixel electrode layer on the source or drain electrode layer.

摘要翻译： 本发明提供一种显示装置及其制造方法，其通过有效地增加材料以及简化步骤来制造。 此外，本发明提供了一种用于形成用于形成显示装置的布线等图案以具有优异的可控性的预定形状的技术。 制造显示装置的方法包括以下步骤：形成疏液区域; 选择性地将激光束照射在疏液区域以形成亲液性区域; 选择性地将含有导电材料的组合物在亲液区域中排出以形成栅极电极层; 在栅电极层上形成栅极绝缘层和半导体层; 在半导体层上排出含有导电材料的组合物，以形成源电极层和漏电极层; 以及在源极或漏极电极层上形成像素电极层。

公开(公告)号：US20100327281A1

公开(公告)日：2010-12-30

申请号：US12820201

申请日：2010-06-22

申请人： Miyako NAKAJIMA ,  Hidekazu MIYAIRI ,  Toshiyuki ISA ,  Erika KATO ,  Mitsuhiro ICHIJO ,  Kazutaka KURIKI ,  Tomokazu YOKOI

发明人： Miyako NAKAJIMA ,  Hidekazu MIYAIRI ,  Toshiyuki ISA ,  Erika KATO ,  Mitsuhiro ICHIJO ,  Kazutaka KURIKI ,  Tomokazu YOKOI

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/6675 ,  H01L29/04 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78669 ,  H01L29/78678 ,  H01L29/78696

摘要： An object is to provide a thin film transistor with small off current, large on current, and high field-effect mobility. A silicon nitride layer and a silicon oxide layer which is formed by oxidizing the silicon nitride layer are stacked as a gate insulating layer, and crystals grow from an interface of the silicon oxide layer of the gate insulating layer to form a microcrystalline semiconductor layer; thus, an inverted staggered thin film transistor is manufactured. Since crystals grow from the gate insulating layer, the thin film transistor can have a high crystallinity, large on current, and high field-effect mobility. In addition, a buffer layer is provided to reduce off current.

摘要翻译： 目的是提供具有小截止电流，大电流和高场效应迁移率的薄膜晶体管。 层叠氮化硅层和通过氧化氮化硅层形成的氧化硅层作为栅极绝缘层，从栅极绝缘层的氧化硅层的界面生长晶体，形成微晶半导体层; 因此，制造了反交错的薄膜晶体管。 由于晶体从栅极绝缘层生长，所以薄膜晶体管可以具有高结晶度，大电流和高的场效应迁移率。 此外，提供缓冲层以减少电流。

公开(公告)号：US20090057672A1

公开(公告)日：2009-03-05

申请号：US12196798

申请日：2008-08-22

申请人： Satoshi KOBAYASHI ,  Ikuko KAWAMATA ,  Koji DAIRIKI ,  Shigeki KOMORI ,  Toshiyuki ISA ,  Shunpei YAMAZAKI

发明人： Satoshi KOBAYASHI ,  Ikuko KAWAMATA ,  Koji DAIRIKI ,  Shigeki KOMORI ,  Toshiyuki ISA ,  Shunpei YAMAZAKI

IPC分类号： H01L29/04 ,  H01L21/336

CPC分类号： H01L29/04 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78696

摘要： A display device including a thin film transistor with high electric characteristics and high reliability, and a method for manufacturing the display device with high mass-productivity. In a display device including an inverted-staggered channel-stop-type thin film transistor, the inverted-staggered channel-stop-type thin film transistor includes a microcrystalline semiconductor film including a channel formation region, and an impurity region containing an impurity element of one conductivity type is selectively provided in a region which is not overlapped with source and drain electrodes, in the channel formation region of the microcrystalline semiconductor film.

摘要翻译： 一种包括具有高电特性和高可靠性的薄膜晶体管的显示装置，以及具有高批量生产率的显示装置的制造方法。 在包括反交错通道停止型薄膜晶体管的显示装置中，反交错通道停止型薄膜晶体管包括包含沟道形成区的微晶半导体膜，以及含有杂质元素的杂质区 在微晶半导体膜的沟道形成区域中，在不与源极和漏极重叠的区域中选择性地提供一种导电型。

公开(公告)号：US20080012076A1

公开(公告)日：2008-01-17

申请号：US11857729

申请日：2007-09-19

申请人： Shunpei YAMAZAKI ,  Osamu NAKAMURA ,  Shinji MAEKAWA ,  Gen FUJII ,  Toshiyuki ISA

发明人： Shunpei YAMAZAKI ,  Osamu NAKAMURA ,  Shinji MAEKAWA ,  Gen FUJII ,  Toshiyuki ISA

IPC分类号： H01L29/786 ,  G03B13/00

CPC分类号： H01L51/0022 ,  G09G3/3208 ,  G09G3/3225 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/0251 ,  H01L27/1285 ,  H01L27/1292 ,  H01L27/3244 ,  H01L51/055 ,  H01L51/529

摘要： The invention provides a display device and a method for manufacturing thereof by increasing a material efficiently as well as simplifying steps. Also, the invention provides a technique for forming a pattern such as a wiring, that is used for forming a display device, to have a predetermined shape with an excellent controllability. The method for manufacturing a display device includes the steps of: forming a lyophobic region; selectively irradiating laser beam in the lyophobic region to form a lyophilic region; selectively discharging a composition, that contains a conductive material, in the lyophilic region to form a gate electrode layer; forming a gate insulating layer and a semiconductor layer over the gate electrode layer; discharging a composition containing a conductive material over the semiconductor layer to form a source electrode layer and a drain electrode layer; and forming a pixel electrode layer on the source or drain electrode layer.

摘要翻译： 本发明提供一种显示装置及其制造方法，其通过有效地增加材料以及简化步骤来制造。 此外，本发明提供了一种用于形成用于形成显示装置的布线等图案以具有优异的可控性的预定形状的技术。 制造显示装置的方法包括以下步骤：形成疏液区域; 选择性地将激光束照射在疏液区域以形成亲液性区域; 选择性地将含有导电材料的组合物在亲液区域中排出以形成栅极电极层; 在栅电极层上形成栅极绝缘层和半导体层; 在半导体层上排出含有导电材料的组合物，以形成源电极层和漏电极层; 以及在源极或漏极电极层上形成像素电极层。

公开(公告)号：US20100136782A1

公开(公告)日：2010-06-03

申请号：US12699984

申请日：2010-02-04

申请人： Toshiyuki ISA ,  Shunpei YAMAZAKI

发明人： Toshiyuki ISA ,  Shunpei YAMAZAKI

IPC分类号： H01L21/768

CPC分类号： H01L21/76877 ,  H01L21/288 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76862 ,  H01L21/76864 ,  H01L21/76874 ,  H01L21/7688 ,  H01L23/5222 ,  H01L23/53242 ,  H01L23/53252 ,  H01L23/5329 ,  H01L24/45 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： In a manufacturing process of a semiconductor device, electroplating and CMP have had a problem of increase in manufacturing costs for forming a wiring. Correspondingly, an opening is formed in a porous insulating film after a mask is formed thereover, and a conductive material containing Ag is dropped into the opening. Further, a first conductive layer is formed by baking the conductive material dropped into the opening by selective irradiation with laser light. Subsequently, a metal film is formed over the entire surface by sputtering, and the mask is removed thereafter to have only the metal film remain over the first conductive layer, thereby forming an embedded wiring layer formed with a stack of the first conductive layer containing Ag and the second conductive layer (metal film).

摘要翻译： 在半导体器件的制造工艺中，电镀和CMP已经出现了用于形成布线的制造成本增加的问题。 相应地，在其上形成掩模之后，在多孔绝缘膜中形成开口，并且含有Ag的导电材料落入开口中。 此外，通过用激光的选择性照射烘烤落入开口中的导电材料，形成第一导电层。 随后，通过溅射在整个表面上形成金属膜，之后除去掩模，仅使金属膜保留在第一导电层上，从而形成嵌入的布线层，该布线层由含有Ag的第一导电层 和第二导电层（金属膜）。

公开(公告)号：US20090267068A1

公开(公告)日：2009-10-29

申请号：US12429486

申请日：2009-04-24

申请人： Koji DAIRIKI ,  Hidekazu MIYAIRI ,  Toshiyuki ISA ,  Akiharu MIYANAGA ,  Takuya HIROHASHI ,  Shunpei YAMAZAKI ,  Takeyoshi WATABE

发明人： Koji DAIRIKI ,  Hidekazu MIYAIRI ,  Toshiyuki ISA ,  Akiharu MIYANAGA ,  Takuya HIROHASHI ,  Shunpei YAMAZAKI ,  Takeyoshi WATABE

IPC分类号： H01L29/786

CPC分类号： H01L27/127 ,  H01J37/32091 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/1288 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78669 ,  H01L29/78678 ,  H01L29/78696

摘要： The thin film transistor includes a gate insulating layer covering a gate electrode, over a substrate having an insulating surface; a semiconductor layer forming a channel formation region, in which a plurality of crystal regions is included in an amorphous structure; an impurity semiconductor layer imparting one conductivity type which forms a source region and a drain region; and a buffer layer formed from an amorphous semiconductor, which is located between the semiconductor layer and the impurity semiconductor layer. The thin film transistor includes the crystal region which includes minute crystal grains and inverted conical or inverted pyramidal grain each of which grows approximately radially from a position away from an interface between the gate insulating layer and the semiconductor layer toward a direction in which the semiconductor layer is deposited in a region which does not reach the impurity semiconductor layer.

摘要翻译： 薄膜晶体管包括覆盖栅电极的栅极绝缘层，在具有绝缘表面的基板上; 形成在非晶结构中包含多个晶体区域的沟道形成区域的半导体层; 赋予形成源极区域和漏极区域的一种导电型的杂质半导体层; 以及由位于半导体层和杂质半导体层之间的非晶半导体形成的缓冲层。 薄膜晶体管包括晶体区域，其包括微小晶粒和倒圆锥形或倒棱锥晶粒，其每个从远离栅极绝缘层和半导体层之间的界面的位置朝向半导体层的方向大致径向地生长 沉积在不到达杂质半导体层的区域中。