公开(公告)号：US20110298000A1

公开(公告)日：2011-12-08

申请号：US13154337

申请日：2011-06-06

申请人： Tsang-Yu LIU ,  Yu-Lin YEN ,  Chuan-Jin SHIU ,  Po-Shen LIN

发明人： Tsang-Yu LIU ,  Yu-Lin YEN ,  Chuan-Jin SHIU ,  Po-Shen LIN

IPC分类号： H01L33/52 ,  H01L31/0203

CPC分类号： H01L27/14623 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L33/44 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/01021 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2224/05552 ,  H01L2924/00

摘要： According to an embodiment of the invention, a chip package is provided, which includes: a substrate having a first surface and a second surface; an optical device between the first surface and the second surface of the substrate; a protection layer formed on the second surface of the substrate, wherein the protection layer has at least an opening; at least a conducting bump formed in the opening of the protection layer and electrically connected to the optical device; and a light shielding layer formed on the protection layer, wherein the light shielding layer is further extended onto a sidewall of the opening of the protection layer.

摘要翻译： 根据本发明的实施例，提供了一种芯片封装，其包括：具有第一表面和第二表面的基板; 在所述基板的所述第一表面和所述第二表面之间的光学装置; 形成在所述基板的第二表面上的保护层，其中所述保护层具有至少一个开口; 至少形成在所述保护层的开口中并电连接到所述光学装置的导电凸起; 以及形成在所述保护层上的遮光层，其中所述遮光层进一步延伸到所述保护层的开口的侧壁上。

公开(公告)号：US20110156074A1

公开(公告)日：2011-06-30

申请号：US12981600

申请日：2010-12-30

申请人： Tsang-Yu LIU ,  Yu-Lin Yen ,  Chuan-Jin Shiu ,  Po-Shen Lin

发明人： Tsang-Yu LIU ,  Yu-Lin Yen ,  Chuan-Jin Shiu ,  Po-Shen Lin

IPC分类号： H01L33/60 ,  H01L33/48

CPC分类号： H01L27/14618 ,  H01L21/76898 ,  H01L23/055 ,  H01L23/16 ,  H01L27/14683 ,  H01L31/0203 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a chip package, including: a chip having a semiconductor device thereon; a cap layer over the semiconductor device; a spacer layer between the chip and the cap layer, wherein the spacer layer surrounds the semiconductor device and forms a cavity between the chip and the cap layer; and an anti-reflective layer between the cap layer and the chip, wherein the anti-reflective layer has a overlapping region with the spacer layer and extends into the cavity. Furthermore, a method for fabricating a chip package is also provided.

摘要翻译： 本发明提供了一种芯片封装，包括：其上具有半导体器件的芯片; 半导体器件上的覆盖层; 在所述芯片和所述盖层之间的间隔层，其中所述间隔层围绕所述半导体器件并且在所述芯片和所述盖层之间形成空腔; 以及在所述盖层和所述芯片之间的抗反射层，其中所述抗反射层具有与所述间隔层的重叠区域并延伸到所述空腔中。 此外，还提供了一种用于制造芯片封装的方法。

公开(公告)号：US20110156191A1

公开(公告)日：2011-06-30

申请号：US12981640

申请日：2010-12-30

申请人： Ta-Hsuan LIN ,  Chuan-Jin SHIU ,  Chia-Ming CHENG ,  Tsang-Yu LIU

发明人： Ta-Hsuan LIN ,  Chuan-Jin SHIU ,  Chia-Ming CHENG ,  Tsang-Yu LIU

IPC分类号： H01L31/0216 ,  H01L31/18

CPC分类号： H01L27/14618 ,  H01L21/76898 ,  H01L23/055 ,  H01L23/16 ,  H01L27/14683 ,  H01L31/0203 ,  H01L2924/0002 ,  H01L2924/00

摘要： The embodiment provides a package structure for a chip and a method for fabricating the same. The package structure for the chip includes a chip having a substrate and a bonding pad structure. The chip has an upper surface and a lower surface. An upper packaging layer covers the upper surface of the chip. A spacer layer is between the upper packaging layer and the chip. A conductive path is electrically connected to the bonding pad structure. An anti-reflective layer is disposed between the spacer layer and the upper packaging layer. An overlapping region is between the anti-reflective layer and the spacer layer.

摘要翻译： 该实施例提供了用于芯片的封装结构及其制造方法。 用于芯片的封装结构包括具有衬底和焊盘结构的芯片。 该芯片具有上表面和下表面。 上包装层覆盖芯片的上表面。 间隔层位于上包装层和芯片之间。 导电路径电连接到接合焊盘结构。 防反射层设置在间隔层和上包装层之间。 重叠区域在抗反射层和间隔层之间。

公开(公告)号：US20120292744A1

公开(公告)日：2012-11-22

申请号：US13476748

申请日：2012-05-21

申请人： Tsang-Yu LIU ,  Chia-Sheng LIN ,  Chia-Ming CHENG ,  Po-Shen LIN

发明人： Tsang-Yu LIU ,  Chia-Sheng LIN ,  Chia-Ming CHENG ,  Po-Shen LIN

IPC分类号： H01L23/544 ,  H01L21/78

CPC分类号： H01L21/78 ,  H01L21/682 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/525 ,  H01L23/544 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/5448 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/014 ,  H01L2924/00

摘要： An embodiment of the invention provides a chip package which includes: a substrate, wherein the substrate is diced from a wafer; a device region formed in the substrate; a conducting layer disposed on the substrate and electrically connected to the device region; an insulating layer disposed between the substrate and the conducting layer; and a material layer formed on the insulating layer, wherein the material layer has a recognition mark, and the recognition mark shows position information of the substrate in the wafer before the substrate is diced from the wafer.

摘要翻译： 本发明的实施例提供了一种芯片封装，其包括：衬底，其中所述衬底从晶片切割; 形成在所述基板中的器件区域; 导电层，其设置在所述基板上并电连接到所述器件区域; 设置在所述基板和所述导电层之间的绝缘层; 以及形成在所述绝缘层上的材料层，其中所述材料层具有识别标记，并且所述识别标记在从所述晶片切割所述基板之前，示出所述晶片中的所述基板的位置信息。

公开(公告)号：US20120261809A1

公开(公告)日：2012-10-18

申请号：US13446954

申请日：2012-04-13

申请人： Yu-Lin YEN ,  Kuo-Hua LIU ,  Yu-Lung HUANG ,  Tsang-Yu LIU ,  Yen-Shih HO

发明人： Yu-Lin YEN ,  Kuo-Hua LIU ,  Yu-Lung HUANG ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC分类号： H01L23/04 ,  H01L21/50

CPC分类号： H01L24/29 ,  H01L23/10 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/29011 ,  H01L2224/29035 ,  H01L2224/29076 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/83191 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2224/83871 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

摘要： An embodiment of the invention provides a manufacturing method of a chip package including: providing a semiconductor wafer having a plurality of device regions separated by a plurality of scribe lines; bonding a package substrate to the semiconductor wafer wherein a spacer layer is disposed therebetween and defines a plurality of cavities respectively exposing the device regions and the spacer layer has a plurality of through holes neighboring the edge of the semiconductor wafer; filling an adhesive material in the through holes wherein the material of the spacer layer is adhesive and different from the adhesive material; and dicing the semiconductor wafer, the package substrate and the spacer layer along the scribe lines to form a plurality of chip packages separated from each other.

摘要翻译： 本发明的实施例提供一种芯片封装的制造方法，包括：提供具有由多个划线分开的多个器件区域的半导体晶片; 将封装衬底接合到半导体晶片，其中间隔层设置在其间并限定分别暴露器件区域并且间隔层具有多个与半导体晶片的边缘相邻的通孔的空腔; 在通孔中填充粘合剂材料，其中间隔层的材料是粘合剂并且不同于粘合剂材料; 并且沿着划线切割半导体晶片，封装衬底和间隔层，以形成彼此分离的多个芯片封装。

公开(公告)号：US20110278734A1

公开(公告)日：2011-11-17

申请号：US13190388

申请日：2011-07-25

申请人： Yu-Lin YEN ,  Chien-Hui CHEN ,  Tsang-Yu LIU ,  Long-Sheng YEOU

发明人： Yu-Lin YEN ,  Chien-Hui CHEN ,  Tsang-Yu LIU ,  Long-Sheng YEOU

IPC分类号： H01L23/48 ,  H01L21/283

CPC分类号： H01L21/76879 ,  B81B7/007 ,  B81B2207/07 ,  B81B2207/092 ,  H01L21/76805 ,  H01L21/76898 ,  H01L23/3178 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/13 ,  H01L24/32 ,  H01L24/94 ,  H01L25/0657 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/13025 ,  H01L2224/9202 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/00

摘要： According to an embodiment of the invention, a chip package is provided. The chip package includes: a substrate having an upper surface and a lower surface; a plurality of conducting pads located under the lower surface of the substrate; a dielectric layer located between the conducting pads; a trench extending from the upper surface towards the lower surface of the substrate; a hole extending from a bottom of the trench towards the lower surface of the substrate, wherein an upper sidewall of the hole inclines to the lower surface of the substrate, and a lower sidewall or a bottom of the hole exposes a portion of the conducting pads; and a conducting layer located in the hole and electrically connected to at least one of the conducting pads.

摘要翻译： 根据本发明的实施例，提供了芯片封装。 芯片封装包括：具有上表面和下表面的基板; 位于所述基板的下表面下方的多个导电垫; 位于导电垫之间的电介质层; 从衬底的上表面延伸到下表面的沟槽; 从所述沟槽的底部延伸到所述衬底的下表面的孔，其中所述孔的上侧壁倾斜到所述衬底的下表面，并且所述孔的下侧壁或底部暴露所述导电垫的一部分 ; 以及导电层，其位于所述孔中并电连接到至少一个所述导电焊盘。

公开(公告)号：US20120319297A1

公开(公告)日：2012-12-20

申请号：US13524985

申请日：2012-06-15

申请人： Yu-Lin YEN ,  Chien-Hui CHEN ,  Tsang-Yu LIU ,  Yen-Shih HO

发明人： Yu-Lin YEN ,  Chien-Hui CHEN ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC分类号： H01L23/48 ,  H01L21/78

CPC分类号： H01L23/3128 ,  H01L23/3114 ,  H01L23/481 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2924/1461 ,  H01L2924/014 ,  H01L2924/00

摘要： An embodiment of the invention provides a chip package which includes: a substrate having a plurality of sides and a plurality of corner regions, wherein each of the corner regions is located at an intersection of at least two of the sides of the substrate; a device region formed in the substrate; a conducting layer disposed on the substrate and electrically connected to the device region; an insulating layer disposed between the substrate and the conducting layer; and a carrier substrate, wherein the substrate is disposed on the carrier substrate, and the substrate has a recess extending towards the carrier substrate in at least one of the corner regions.

摘要翻译： 本发明的实施例提供一种芯片封装，其包括：具有多个侧面和多个拐角区域的基板，其中每个所述拐角区域位于所述基板的至少两个侧面的相交处; 形成在所述基板中的器件区域; 导电层，其设置在所述基板上并电连接到所述器件区域; 设置在所述基板和所述导电层之间的绝缘层; 以及载体基板，其中所述基板设置在所述载体基板上，并且所述基板具有在至少一个所述拐角区域中朝向所述载体基板延伸的凹部。

公开(公告)号：US20110278735A1

公开(公告)日：2011-11-17

申请号：US13190408

申请日：2011-07-25

申请人： Yu-Lin YEN ,  Chien-Hui CHEN ,  Tsang-Yu LIU ,  Long-Sheng YEOU

发明人： Yu-Lin YEN ,  Chien-Hui CHEN ,  Tsang-Yu LIU ,  Long-Sheng YEOU

IPC分类号： H01L23/48 ,  H01L21/283

CPC分类号： H01L21/76879 ,  B81B7/007 ,  B81B2207/07 ,  B81B2207/092 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/32 ,  H01L24/94 ,  H01L2221/68377 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/05552

摘要： According to an embodiment of the invention, a chip package is provided. The chip package includes: a substrate having an upper surface and a lower surface; a plurality of conducting pads located under the lower surface of the substrate; a dielectric layer located between the conducting pads; a trench extending from the upper surface towards the lower surface of the substrate; a hole extending from a bottom of the trench towards the lower surface of the substrate, wherein a sidewall of the hole is substantially perpendicular to the lower surface of the substrate, and the sidewall or a bottom of the hole exposes a portion of the conducting pads; and a conducting layer located in the hole and electrically connected to at least one of the conducting pads.

摘要翻译： 根据本发明的实施例，提供了芯片封装。 芯片封装包括：具有上表面和下表面的基板; 位于所述基板的下表面下方的多个导电垫; 位于导电垫之间的电介质层; 从衬底的上表面延伸到下表面的沟槽; 从所述沟槽的底部延伸到所述衬底的下表面的孔，其中所述孔的侧壁基本上垂直于所述衬底的下表面，并且所述孔的侧壁或所述底部露出所述导电垫的一部分 ; 以及导电层，其位于所述孔中并电连接到至少一个所述导电焊盘。

公开(公告)号：US20110285032A1

公开(公告)日：2011-11-24

申请号：US13204603

申请日：2011-08-05

申请人： Yu-Lin YEN ,  Chien-Hui CHEN ,  Tsang-Yu LIU ,  Long-Sheng YEOU

发明人： Yu-Lin YEN ,  Chien-Hui CHEN ,  Tsang-Yu LIU ,  Long-Sheng YEOU

IPC分类号： H01L23/498

CPC分类号： H01L23/49827 ,  H01L21/561 ,  H01L21/76805 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/481 ,  H01L24/06 ,  H01L24/32 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0557 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/05552

摘要： According to an embodiment of the invention, a chip package is provided. The chip package includes a substrate having an upper surface and a lower surface, a plurality of conducting pads located in the substrate or under the lower surface thereof, a dielectric layer located between the conducting pads, a hole extending from the upper surface towards the lower surface of the substrate and exposing a portion of the conducting pads, and a conducting layer located in the hole and electrically contacting the conducting pads.

摘要翻译： 根据本发明的实施例，提供了芯片封装。 芯片封装包括具有上表面和下表面的衬底，位于衬底中或其下表面下方的多个导电焊盘，位于导电焊盘之间的介电层，从上表面向下延伸的孔 表面并暴露一部分导电焊盘，以及导电层，位于孔中并与导电焊盘电接触。

公开(公告)号：US20120112329A1

公开(公告)日：2012-05-10

申请号：US13350690

申请日：2012-01-13

申请人： Yu-Lin YEN ,  Shih-Ming CHEN ,  Hsi-Chien LIN ,  Yu-Lung HUANG ,  Tsang-Yu LIU

发明人： Yu-Lin YEN ,  Shih-Ming CHEN ,  Hsi-Chien LIN ,  Yu-Lung HUANG ,  Tsang-Yu LIU

IPC分类号： H01L23/495

CPC分类号： H01L31/0203 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/481 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14683 ,  H01L27/14685 ,  H01L31/048 ,  H01L2224/16 ,  H01L2924/1461 ,  Y02E10/50 ,  H01L2924/00

摘要： An embodiment of the invention provides a chip package, which includes: a semiconductor substrate having a device region and a non-device region neighboring the device region; a package layer disposed on the semiconductor substrate; a spacing layer disposed between the semiconductor substrate and the package layer and surrounding the device region and the non-device region; a ring structure disposed between the semiconductor substrate and the package layer, and between the spacing layer and the device region, and surrounding a portion of the non-device region; and an auxiliary pattern including a hollow pattern formed in the spacing layer or the ring structure, a material pattern located between the spacing layer and the device region, or combinations thereof.

摘要翻译： 本发明的一个实施例提供了一种芯片封装，其包括：半导体衬底，具有与器件区域相邻的器件区域和非器件区域; 封装层，设置在所述半导体衬底上; 间隔层，设置在所述半导体衬底和所述封装层之间并且围绕所述器件区域和所述非器件区域; 设置在所述半导体衬底和所述封装层之间以及所述间隔层和所述器件区域之间并围绕所述非器件区域的一部分的环形结构; 以及包括形成在间隔层或环结构中的中空图案的辅助图案，位于间隔层和器件区域之间的材料图案，或其组合。