公开(公告)号：US20120261809A1

公开(公告)日：2012-10-18

申请号：US13446954

申请日：2012-04-13

申请人： Yu-Lin YEN ,  Kuo-Hua LIU ,  Yu-Lung HUANG ,  Tsang-Yu LIU ,  Yen-Shih HO

发明人： Yu-Lin YEN ,  Kuo-Hua LIU ,  Yu-Lung HUANG ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC分类号： H01L23/04 ,  H01L21/50

CPC分类号： H01L24/29 ,  H01L23/10 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/29011 ,  H01L2224/29035 ,  H01L2224/29076 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/83191 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2224/83871 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

摘要： An embodiment of the invention provides a manufacturing method of a chip package including: providing a semiconductor wafer having a plurality of device regions separated by a plurality of scribe lines; bonding a package substrate to the semiconductor wafer wherein a spacer layer is disposed therebetween and defines a plurality of cavities respectively exposing the device regions and the spacer layer has a plurality of through holes neighboring the edge of the semiconductor wafer; filling an adhesive material in the through holes wherein the material of the spacer layer is adhesive and different from the adhesive material; and dicing the semiconductor wafer, the package substrate and the spacer layer along the scribe lines to form a plurality of chip packages separated from each other.

摘要翻译： 本发明的实施例提供一种芯片封装的制造方法，包括：提供具有由多个划线分开的多个器件区域的半导体晶片; 将封装衬底接合到半导体晶片，其中间隔层设置在其间并限定分别暴露器件区域并且间隔层具有多个与半导体晶片的边缘相邻的通孔的空腔; 在通孔中填充粘合剂材料，其中间隔层的材料是粘合剂并且不同于粘合剂材料; 并且沿着划线切割半导体晶片，封装衬底和间隔层，以形成彼此分离的多个芯片封装。

公开(公告)号：US20120319297A1

公开(公告)日：2012-12-20

申请号：US13524985

申请日：2012-06-15

申请人： Yu-Lin YEN ,  Chien-Hui CHEN ,  Tsang-Yu LIU ,  Yen-Shih HO

发明人： Yu-Lin YEN ,  Chien-Hui CHEN ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC分类号： H01L23/48 ,  H01L21/78

CPC分类号： H01L23/3128 ,  H01L23/3114 ,  H01L23/481 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2924/1461 ,  H01L2924/014 ,  H01L2924/00

摘要： An embodiment of the invention provides a chip package which includes: a substrate having a plurality of sides and a plurality of corner regions, wherein each of the corner regions is located at an intersection of at least two of the sides of the substrate; a device region formed in the substrate; a conducting layer disposed on the substrate and electrically connected to the device region; an insulating layer disposed between the substrate and the conducting layer; and a carrier substrate, wherein the substrate is disposed on the carrier substrate, and the substrate has a recess extending towards the carrier substrate in at least one of the corner regions.

摘要翻译： 本发明的实施例提供一种芯片封装，其包括：具有多个侧面和多个拐角区域的基板，其中每个所述拐角区域位于所述基板的至少两个侧面的相交处; 形成在所述基板中的器件区域; 导电层，其设置在所述基板上并电连接到所述器件区域; 设置在所述基板和所述导电层之间的绝缘层; 以及载体基板，其中所述基板设置在所述载体基板上，并且所述基板具有在至少一个所述拐角区域中朝向所述载体基板延伸的凹部。

公开(公告)号：US20120112329A1

公开(公告)日：2012-05-10

申请号：US13350690

申请日：2012-01-13

申请人： Yu-Lin YEN ,  Shih-Ming CHEN ,  Hsi-Chien LIN ,  Yu-Lung HUANG ,  Tsang-Yu LIU

发明人： Yu-Lin YEN ,  Shih-Ming CHEN ,  Hsi-Chien LIN ,  Yu-Lung HUANG ,  Tsang-Yu LIU

IPC分类号： H01L23/495

CPC分类号： H01L31/0203 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/481 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14683 ,  H01L27/14685 ,  H01L31/048 ,  H01L2224/16 ,  H01L2924/1461 ,  Y02E10/50 ,  H01L2924/00

摘要： An embodiment of the invention provides a chip package, which includes: a semiconductor substrate having a device region and a non-device region neighboring the device region; a package layer disposed on the semiconductor substrate; a spacing layer disposed between the semiconductor substrate and the package layer and surrounding the device region and the non-device region; a ring structure disposed between the semiconductor substrate and the package layer, and between the spacing layer and the device region, and surrounding a portion of the non-device region; and an auxiliary pattern including a hollow pattern formed in the spacing layer or the ring structure, a material pattern located between the spacing layer and the device region, or combinations thereof.

摘要翻译： 本发明的一个实施例提供了一种芯片封装，其包括：半导体衬底，具有与器件区域相邻的器件区域和非器件区域; 封装层，设置在所述半导体衬底上; 间隔层，设置在所述半导体衬底和所述封装层之间并且围绕所述器件区域和所述非器件区域; 设置在所述半导体衬底和所述封装层之间以及所述间隔层和所述器件区域之间并围绕所述非器件区域的一部分的环形结构; 以及包括形成在间隔层或环结构中的中空图案的辅助图案，位于间隔层和器件区域之间的材料图案，或其组合。

公开(公告)号：US20120267780A1

公开(公告)日：2012-10-25

申请号：US13452595

申请日：2012-04-20

申请人： Bing-Siang CHEN ,  Chien-Hui CHEN ,  Shu-Ming CHANG ,  Tsang-Yu LIU ,  Yen-Shih HO

发明人： Bing-Siang CHEN ,  Chien-Hui CHEN ,  Shu-Ming CHANG ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC分类号： H01L23/498 ,  H01L21/78

CPC分类号： H01L21/78 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06582 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00

摘要： An embodiment of the invention provides a chip package which includes: a first chip; a second chip disposed on the first chip, wherein a side surface of the second chip is a chemically-etched surface; and a bonding bulk disposed between the first chip and the second chip such that the first chip and the second chip are bonded with each other.

摘要翻译： 本发明的实施例提供一种芯片封装，其包括：第一芯片; 设置在所述第一芯片上的第二芯片，其中所述第二芯片的侧表面是化学蚀刻表面; 以及设置在所述第一芯片和所述第二芯片之间的结合体，使得所述第一芯片和所述第二芯片彼此结合。

公开(公告)号：US20120313222A1

公开(公告)日：2012-12-13

申请号：US13178375

申请日：2011-07-07

申请人： Hung-Jen LEE ,  Shu-Ming CHANG ,  Chen-Han CHIANG ,  Tsang-Yu LIU ,  Yen-Shih HO

发明人： Hung-Jen LEE ,  Shu-Ming CHANG ,  Chen-Han CHIANG ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC分类号： H01L29/02 ,  H01L21/78

CPC分类号： H01L23/544 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/13 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2223/5446 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/131 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29124 ,  H01L2224/2957 ,  H01L2224/296 ,  H01L2224/3003 ,  H01L2224/30155 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83125 ,  H01L2224/83127 ,  H01L2224/83192 ,  H01L2224/83895 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2924/00

摘要： An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defined thereon, wherein the predetermined scribe lines define a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively and a cutting support structure located on peripheries of the chip support rings, and the spacing layer has a gap pattern separating the cutting support structure from the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure.

摘要翻译： 本发明的一个实施例提供了一种芯片封装结构的制造方法，包括：提供具有限定在其上的多个预定划线的第一基板，其中，所述预定划线限定多个器件区域; 将第二基板接合到第一基板，其中间隔层设置在其间并且分别具有位于装置区域中的多个芯片支撑环和位于芯片支撑环的周边的切割支撑结构，并且间隔层具有 将切割支撑结构与芯片支撑环分离的间隙图案; 以及切割所述第一基板和所述第二基板以形成多个芯片封装。 本发明的另一实施例提供一种芯片封装结构。

公开(公告)号：US20120313261A1

公开(公告)日：2012-12-13

申请号：US13492649

申请日：2012-06-08

申请人： Hung-Jen LEE ,  Shu-Ming CHANG ,  Chen-Han CHIANG ,  Tsang-Yu LIU ,  Yen-Shih HO

发明人： Hung-Jen LEE ,  Shu-Ming CHANG ,  Chen-Han CHIANG ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC分类号： H01L23/48 ,  H01L21/78

CPC分类号： H01L23/544 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/13 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2223/5446 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/131 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29124 ,  H01L2224/2957 ,  H01L2224/296 ,  H01L2224/3003 ,  H01L2224/30155 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83125 ,  H01L2224/83127 ,  H01L2224/83192 ,  H01L2224/83895 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2924/00

摘要： An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defining a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively, a cutting support structure located on peripheries of the chip support rings, a plurality of stop rings surrounding the chip support rings respectively, wherein a gap pattern separating the stop rings from the cutting support structure and the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure.

摘要翻译： 本发明的一个实施例提供了一种芯片封装结构的制造方法，包括：提供具有限定多个器件区域的多个预定划线的第一衬底; 将第二基板接合到第一基板，其中间隔层设置在其间并且分别具有位于装置区域中的多个芯片支撑环，位于芯片支撑环的周边的切割支撑结构，围绕 所述芯片支撑环分别具有将所述止动环与所述切割支撑结构和所述芯片支撑环分离的间隙图案; 以及切割所述第一基板和所述第二基板以形成多个芯片封装。 本发明的另一实施例提供一种芯片封装结构。

公开(公告)号：US20120241923A1

公开(公告)日：2012-09-27

申请号：US13219468

申请日：2011-08-26

申请人： Yao-Hsiang CHEN ,  Tsang-Yu LIU ,  Yen-Shih HO ,  Shu-Ming CHANG

发明人： Yao-Hsiang CHEN ,  Tsang-Yu LIU ,  Yen-Shih HO ,  Shu-Ming CHANG

IPC分类号： H01L21/60 ,  H01L23/498

CPC分类号： H01L23/552 ,  H01L21/71 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/06155 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13144 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552

摘要： An IC wafer and the method of making the IC wafer, the IC wafer includes an integrated circuit layer having a plurality of solder pads and an insulated layer arranged thereon, a plurality of through holes cut through the insulated layer corresponding to the solder pads respectively for the implantation of a package layer, and an electromagnetic shielding layer formed on the top surface of the insulated layer and electrically isolated from the solder pads of the integrated circuit layer for electromagnetic sheilding. Thus, the integrated circuit does not require any further shielding mask, simplifying the fabrication. Further, the design of the through holes facilitates further packaging process.

摘要翻译： IC晶片和IC晶片的制造方法，IC晶片包括具有多个焊盘和设置在其上的绝缘层的集成电路层，多个贯穿相应于焊盘的绝缘层的通孔，分别用于 封装层的注入和形成在绝缘层的顶表面上并与用于电磁结构的集成电路层的焊盘电隔离的电磁屏蔽层。 因此，集成电路不需要任何进一步的屏蔽掩模，从而简化制造。 此外，通孔的设计有助于进一步的包装过程。

公开(公告)号：US20120184070A1

公开(公告)日：2012-07-19

申请号：US13352234

申请日：2012-01-17

申请人： Chien-Hui CHEN ,  Ming-Kun YANG ,  Tsang-Yu LIU ,  Yen-Shih HO

发明人： Chien-Hui CHEN ,  Ming-Kun YANG ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC分类号： H01L21/78

CPC分类号： H01L21/76898 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/73253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/00

摘要： An embodiment of the invention provides a method for forming a chip package which includes: providing a substrate having a first surface and a second surface, wherein at least two conducting pads are disposed on the first surface of the substrate; partially removing the substrate from the second surface of the substrate to form at least two holes extending towards the first surface, wherein the holes correspondingly and respectively align with one of the conducting pads; after the holes are formed, partially removing the substrate from the second substrate to form at least a recess extending towards the first surface, wherein the recess overlaps with the holes; forming an insulating layer on a sidewall and a bottom of the trench and on sidewalls of the holes; and forming a conducting layer on the insulating layer, wherein the conducting layer electrically contacts with one of the conducting pads.

摘要翻译： 本发明的一个实施例提供了一种用于形成芯片封装的方法，其包括：提供具有第一表面和第二表面的衬底，其中至少两个导电焊盘设置在衬底的第一表面上; 从衬底的第二表面部分地去除衬底以形成朝向第一表面延伸的至少两个孔，其中，孔对应并分别对准导电焊盘中的一个; 在形成所述孔之后，从所述第二基板部分地移除所述基板以形成朝向所述第一表面延伸的至少一个凹部，其中所述凹部与所述孔重叠; 在沟槽的侧壁和底部以及孔的侧壁上形成绝缘层; 以及在所述绝缘层上形成导电层，其中所述导电层与所述导电焊盘之一电接触。

公开(公告)号：US20120168939A1

公开(公告)日：2012-07-05

申请号：US13340162

申请日：2011-12-29

申请人： Shu-Ming CHANG ,  Tsang-Yu LIU ,  Yen-Shih HO

发明人： Shu-Ming CHANG ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC分类号： H01L23/498 ,  H01L21/60

CPC分类号： H01L25/50 ,  B81C1/00238 ,  B81C2203/0785 ,  B81C2203/0792 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/10 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/73 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05669 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/14517 ,  H01L2224/17517 ,  H01L2224/73103 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

摘要： An embodiment of the invention provides a chip package which includes: a first chip; a second chip disposed on the first chip; a hole extending from a surface of the first chip towards the second chip; a conducting layer disposed on the surface of the first chip and extending into the hole and electrically connected to a conducting region or a doped region in the first chip; and a support bulk disposed between the first chip and the second chip, wherein the support bulk substantially and/or completely covers a bottom of the hole.

摘要翻译： 本发明的实施例提供一种芯片封装，其包括：第一芯片; 设置在第一芯片上的第二芯片; 从所述第一芯片的表面向所述第二芯片延伸的孔; 导电层，设置在所述第一芯片的表面上并延伸到所述孔中并电连接到所述第一芯片中的导电区域或掺杂区域; 以及设置在所述第一芯片和所述第二芯片之间的支撑体，其中所述支撑体基本上和/或完全覆盖所述孔的底部。

公开(公告)号：US20120193811A1

公开(公告)日：2012-08-02

申请号：US13360435

申请日：2012-01-27

申请人： Ming-Kun YANG ,  Tsang-Yu LIU ,  Yen-Shih HO

发明人： Ming-Kun YANG ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC分类号： H01L23/498 ,  H01L21/768

CPC分类号： H01L23/492 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/12044 ,  H05K2201/10378 ,  H01L2924/00

摘要： An embodiment of the invention provides an interposer which includes: a substrate having a first surface and a second surface; a first hole extending from the first surface towards the second surface; a second hole extending from the first surface towards the second surface, wherein a width of the first hole is different from a width of the second hole; an insulating layer located on the substrate and extending onto a sidewall of the first hole and a sidewall of the second hole; and a conducting layer located on the insulating layer on the substrate and extending onto the sidewall of the first hole, wherein there is substantially no conducting layer in the second hole.

摘要翻译： 本发明的实施例提供一种插入器，其包括：具有第一表面和第二表面的基板; 从所述第一表面朝向所述第二表面延伸的第一孔; 从所述第一表面朝向所述第二表面延伸的第二孔，其中所述第一孔的宽度与所述第二孔的宽度不同; 位于所述基板上并延伸到所述第一孔的侧壁和所述第二孔的侧壁上的绝缘层; 以及导电层，其位于所述基板上的所述绝缘层上并且延伸到所述第一孔的侧壁上，其中在所述第二孔中基本上没有导电层。