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    Polarization-doped field effect transistors (POLFETS) and materials and methods for making the same
    3.
    发明授权
    Polarization-doped field effect transistors (POLFETS) and materials and methods for making the same 有权
    极化掺杂场效应晶体管（POLFETS）及其制作方法

    公开(公告)号：US07525130B2

    公开(公告)日：2009-04-28

    申请号：US11241804

    申请日：2005-09-29

    申请人： Umesh K. Mishra ,  Huili Xing ,  Debdeep Jena ,  Siddharth Rajan

    发明人： Umesh K. Mishra ,  Huili Xing ,  Debdeep Jena ,  Siddharth Rajan

    IPC分类号： H01L31/00

    CPC分类号： H01L29/812 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/7783 ,  H01L29/7787

    摘要： Novel GaN/AlGaN metal-semiconductor field-effect transistor (MESFET) structures grown without any impurity doping in the channel. A high-mobility polarization-induced bulk channel charge is created by grading the channel region linearly from GaN to Al0.3Ga0.7N over a distance, e.g., 1000 Å. A polarization-doped field effect transistor (PolFET) was fabricated and tested under DC and RF conditions. A current density of 850 mA/mm and transconductance of 93 mS/mm was observed under DC conditions. Small-signal characterization of 0.7 μm gate length devices had a cutoff frequency, fτ=19 GHz, and a maximum oscillation of fmax=46 GHz. The PolFETs perform better than comparable MESFETs with impurity-doped channels, and are suitable for high microwave power applications. An important advantage of these devices over AlGaN/GaN HEMTs is that the transconductance vs. gate voltage profile can be tailored by compositional grading for better large-signal linearity.

    摘要翻译： 新型GaN / AlGaN金属半导体场效应晶体管（MESFET）结构在通道中没有任何杂质掺杂生长。 通过在一定距离（例如）1000处将通道区域从GaN线性地分级至Al 0.3 Ga 0.7 N来产生高迁移率极化诱导的体沟道电荷。 在DC和RF条件下制造和测试偏振掺杂场效应晶体管（PolFET）。 在直流条件下观察到电流密度为850mA / mm，跨导为93mS / mm。 0.7mm门极长度器件的小信号表征具有截止频率ftau = 19GHz，fmax = 46GHz的最大振荡。 PolFET比具有杂质掺杂通道的可比MESFET性能更好，适用于高微波功率应用。 这些器件对AlGaN / GaN HEMT的一个重要优点是跨导与栅极电压分布可以通过组合分级来定制，以获得更好的大信号线性度。

    METHOD TO FABRICATE III-N SEMICONDUCTOR DEVICES ON THE N-FACE OF LAYERS WHICH ARE GROWN IN THE III-FACE DIRECTION USING WAFER BONDING AND SUBSTRATE REMOVAL
    6.
    发明申请
    METHOD TO FABRICATE III-N SEMICONDUCTOR DEVICES ON THE N-FACE OF LAYERS WHICH ARE GROWN IN THE III-FACE DIRECTION USING WAFER BONDING AND SUBSTRATE REMOVAL 审中-公开
    使用波形焊接和基板去除在III面形成的层的N面上制造III-N半导体器件的方法

    公开(公告)号：US20090085065A1

    公开(公告)日：2009-04-02

    申请号：US12059907

    申请日：2008-03-31

    申请人： Umesh K. Mishra ,  Lee S. McCarthy ,  Chang Soo Suh ,  Siddharth Rajan

    发明人： Umesh K. Mishra ,  Lee S. McCarthy ,  Chang Soo Suh ,  Siddharth Rajan

    IPC分类号： H01L29/778 ,  H01L21/18 ,  H01L21/20

    CPC分类号： H01L29/66462 ,  H01L21/187 ,  H01L29/045 ,  H01L29/2003 ,  H01L29/7783

    摘要： A method for fabricating III-N semiconductor devices on the N-face of layers comprising (a) growing a III-nitride semiconductor device structure in a Ga-polar direction on a substrate, (b) attaching a Ga face of the III-nitride semiconductor device structure to a host substrate, and (c) removing the substrate to expose the N-face surface of the III-nitride semiconductor device structure. An N-polar (000-1) oriented III-nitride semiconductor device is also disclosed, comprising one or more (000-1) oriented nitride layers, each having an N-face opposite a group III-face, wherein at least one N-face is an at least partially exposed N-face, and a host substrate attached to one of the group III-faces.

    摘要翻译： 一种用于在层的N面上制造III-N半导体器件的方法，包括（a）在衬底上生长Ga极性方向上的III族氮化物半导体器件结构，（b）将III族氮化物的Ga面 半导体器件结构，以及（c）去除衬底以露出III族氮化物半导体器件结构的N面。 还公开了一种N极（000-1）取向的III族氮化物半导体器件，其包括一个或多个（000-1）取向的氮化物层，每个具有与III族面相反的N面，其中至少一个N 表面是至少部分暴露的N面，以及附着到III组面中的一个的主体衬底。

    Heterostructure device and associated method
    7.
    发明授权
    Heterostructure device and associated method 有权
    异质结构装置及相关方法

    公开(公告)号：US08159002B2

    公开(公告)日：2012-04-17

    申请号：US11961532

    申请日：2007-12-20

    申请人： Vinayak Tilak ,  Alexei Vertiatchikh ,  Kevin Sean Matocha ,  Peter Micah Sandvik ,  Siddharth Rajan

    发明人： Vinayak Tilak ,  Alexei Vertiatchikh ,  Kevin Sean Matocha ,  Peter Micah Sandvik ,  Siddharth Rajan

    IPC分类号： H01L29/66

    CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/207

    摘要： A heterostructure device includes a semiconductor multi-layer structure that has a first region, a second region and a third region. The first region is coupled to a source electrode and the second region is coupled to a drain electrode. The third region is disposed between the first region and the second region. The third region provides a switchable electrically conductive pathway from the source electrode to the drain electrode. The third region includes iodine ions. A system includes a heterostructure field effect transistor that includes the device.

    摘要翻译： 异质结构器件包括具有第一区域，第二区域和第三区域的半导体多层结构。 第一区域耦合到源电极，第二区域耦合到漏电极。 第三区域设置在第一区域和第二区域之间。 第三区域提供从源电极到漏电极的可切换导电路径。 第三区域包括碘离子。 一种系统包括包括该器件的异质结构场效应晶体管。

    HETEROSTRUCTURE DEVICE AND ASSOCIATED METHOD
    8.
    发明申请
    HETEROSTRUCTURE DEVICE AND ASSOCIATED METHOD 有权
    异体结构设备及相关方法

    公开(公告)号：US20090159929A1

    公开(公告)日：2009-06-25

    申请号：US11961532

    申请日：2007-12-20

    申请人： Vinayak Tilak ,  Alexei Vertiatchikh ,  Kevin Sean Matocha ,  Peter Micah Sandvik ,  Siddharth Rajan

    发明人： Vinayak Tilak ,  Alexei Vertiatchikh ,  Kevin Sean Matocha ,  Peter Micah Sandvik ,  Siddharth Rajan

    IPC分类号： H01L29/78 ,  H01L21/335

    CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/207

    摘要： A heterostructure device includes a semiconductor multi-layer structure that has a first region, a second region and a third region. The first region is coupled to a source electrode and the second region is coupled to a drain electrode. The third region is disposed between the first region and the second region. The third region provides a switchable electrically conductive pathway from the source electrode to the drain electrode. The third region includes iodine ions. A system includes a heterostructure field effect transistor that includes the device.

    摘要翻译： 异质结构器件包括具有第一区域，第二区域和第三区域的半导体多层结构。 第一区域耦合到源电极，第二区域耦合到漏电极。 第三区域设置在第一区域和第二区域之间。 第三区域提供从源电极到漏电极的可切换导电路径。 第三区域包括碘离子。 一种系统包括包括该器件的异质结构场效应晶体管。

    Heterostructure device and associated method
    9.
    发明授权
    Heterostructure device and associated method 有权
    异质结构装置及相关方法

    公开(公告)号：US08697506B2

    公开(公告)日：2014-04-15

    申请号：US13418566

    申请日：2012-03-13

    申请人： Vinayak Tilak ,  Alexei Vertiatchikh ,  Kevin Sean Matocha ,  Peter Micah Sandvik ,  Siddharth Rajan

    发明人： Vinayak Tilak ,  Alexei Vertiatchikh ,  Kevin Sean Matocha ,  Peter Micah Sandvik ,  Siddharth Rajan

    IPC分类号： H01L21/335

    CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/207

    摘要： A method of manufacturing a heterostructure device is provided that includes implantation of ions into a portion of a surface of a multi-layer structure. Iodine ions are implanted between a first region and a second region to form a third region. A charge is depleted from the two dimensional electron gas (2DEG) channel in the third region to form a reversibly electrically non-conductive pathway from the first region to the second region. On applying a voltage potential to a gate electrode proximate to the third region allows electrical current to flow from the first region to the second region.

    摘要翻译： 提供了一种制造异质结构器件的方法，其包括将离子注入到多层结构的表面的一部分中。 碘离子注入第一区域和第二区域之间以形成第三区域。 电荷从第三区域中的二维电子气（2DEG）通道中消耗，以形成从第一区域到第二区域的可逆的非导电通路。 在向靠近第三区域的栅电极施加电压电位时，允许电流从第一区域流到第二区域。