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    Core array and periphery isolation technique
    1.
    发明授权
    Core array and periphery isolation technique 失效
    核心阵列和外围隔离技术

    公开(公告)号：US06004862A

    公开(公告)日：1999-12-21

    申请号：US8320

    申请日：1998-01-20

    申请人： Unsoon Kim ,  Hung-Sheng Chen ,  Kashmir Sahota ,  Yu Sun

    发明人： Unsoon Kim ,  Hung-Sheng Chen ,  Kashmir Sahota ,  Yu Sun

    IPC分类号： H01L21/762 ,  H01L21/76

    CPC分类号： H01L21/76202 ,  H01L21/76224

    摘要： A process for forming a semiconductor integrated circuit with a core area densely populated with active devices and with a periphery area less densely populated with active devices as compared to the core area, comprising the steps of: forming a first layer of first insulator material above a semiconductor substrate having a core area and a periphery area, wherein the first insulator material constitutes a polish stop for polishing processes and also as an oxidation barrier; patterning the first layer of first insulator material to expose first portions of the semiconductor substrate substantially only in the core area while using the first insulator material to substantially mask the periphery area; forming a plurality of trenches into the exposed first portions of semiconductor substrate in the core area; filling the plurality of trenches with an insulator; polishing down to the first layer of first insulator material; removing the first layer of first insulator material; forming a second layer of first insulator material over the core and periphery areas; forming openings down into the second layer of first insulator material to expose second portions of the semiconductor substrate substantially only in the periphery area while using the second layer to substantially mask the core area; and forming an isolation region in the exposed second portions of the semiconductor substrate.

    摘要翻译： 一种用于形成半导体集成电路的方法，所述半导体集成电路具有密集地填充有有源器件的核心区域，并且与所述核心区域相比具有较少密集地填充有源器件的外围区域，包括以下步骤：在第一绝缘体材料的上方形成第一层 具有芯区域和周边区域的半导体衬底，其中所述第一绝缘体材料构成用于抛光工艺的抛光止挡件以及氧化屏障; 图案化第一绝缘体材料层，以在使用第一绝缘体材料基本上遮蔽周边区域的同时，在半导体衬底的基本上仅在芯部区域露出第一部分; 在芯区域中的半导体衬底的暴露的第一部分中形成多个沟槽; 用绝缘体填充多个沟槽; 抛光到第一绝缘体材料层; 去除第一绝缘体材料的第一层; 在所述芯和外围区域上形成第二绝缘体材料层; 将第一绝缘体材料的第二层向下形成开口，以便在使用第二层基本上掩蔽核心区域时，基本上只在周边区域露出半导体衬底的第二部分; 以及在半导体衬底的暴露的第二部分中形成隔离区。

    Method for controlling poly 1 thickness and uniformity in a memory array fabrication process
    5.
    发明授权
    Method for controlling poly 1 thickness and uniformity in a memory array fabrication process 有权
    用于控制存储器阵列制造工艺中聚1厚度和均匀性的方法

    公开(公告)号：US07294573B1

    公开(公告)日：2007-11-13

    申请号：US11035188

    申请日：2005-01-13

    申请人： Krishnashree Achuthan ,  Unsoon Kim ,  Kashmir Sahota ,  Patriz C. Regalado

    发明人： Krishnashree Achuthan ,  Unsoon Kim ,  Kashmir Sahota ,  Patriz C. Regalado

    IPC分类号： H01L21/302 ,  H01L21/461

    CPC分类号： H01L21/7684

    摘要： According to one exemplary embodiment, a method includes planarizing a layer of polysilicon situated over field oxide regions on a substrate to form polysilicon segments, where the polysilicon segments have top surfaces that are substantially planar with top surfaces of the field oxide regions, and where the field oxide regions have a first height and the polysilicon segments have a first thickness. The method further includes removing a hard mask over a peripheral region of the substrate. According to this exemplary embodiment, the method further includes etching the polysilicon segments to cause the polysilicon segments to have a second thickness, which causes the top surfaces of the polysilicon segments to be situated below the top surfaces of the field oxide regions. The polysilicon segments can be etched by using a wet etch process. The polysilicon segments are situated in a core region of the substrate.

    摘要翻译： 根据一个示例性实施例，一种方法包括将位于衬底上的场氧化物区域上的多晶硅层平坦化以形成多晶硅段，其中多晶硅段具有与场氧化物区域的顶表面基本上平面的顶表面， 场氧化物区域具有第一高度，并且多晶硅段具有第一厚度。 该方法还包括在衬底的周边区域上去除硬掩模。 根据该示例性实施例，该方法还包括蚀刻多晶硅段以使多晶硅段具有第二厚度，这导致多晶硅段的顶表面位于场氧化物区的顶表面之下。 可以通过使用湿蚀刻工艺来蚀刻多晶硅段。 多晶硅段位于衬底的芯区域中。

    Method and system for providing a contact on a semiconductor device
    6.
    发明授权
    Method and system for providing a contact on a semiconductor device 失效
    用于在半导体器件上提供接触的方法和系统

    公开(公告)号：US6103593A

    公开(公告)日：2000-08-15

    申请号：US23836

    申请日：1998-02-13

    申请人： Angela T. Hui ,  Hung-Sheng Chen ,  Unsoon Kim

    发明人： Angela T. Hui ,  Hung-Sheng Chen ,  Unsoon Kim

    IPC分类号： H01L21/762 ,  H01L21/768 ,  H01L21/76 ,  H01L21/44

    CPC分类号： H01L21/76802 ,  H01L21/76237 ,  H01L21/76834 ,  Y10S438/97

    摘要： A method for providing at least one contact on a semiconductor is disclosed. The semiconductor includes a plurality of isolation structures. The method and system include providing an etch-stop layer in direct contact with the semiconductor, providing a dielectric layer over the etch-stop layer, and etching through the dielectric layer and a portion of the etch-stop layer. A portion of the semiconductor in proximity with one of the plurality of isolation structures is not exposed during the etch.

    摘要翻译： 公开了一种在半导体上提供至少一个接触的方法。 半导体包括多个隔离结构。 该方法和系统包括提供与半导体直接接触的蚀刻停止层，在蚀刻停止层上方提供介电层，以及蚀刻穿过介电层和蚀刻停止层的一部分。 在蚀刻期间，与多个隔离结构之一接近的半导体的一部分不暴露。

    Isolation boundaries in flash memory cores
    8.
    发明授权
    Isolation boundaries in flash memory cores 失效
    闪存内核中的隔离边界

    公开(公告)号：US06040597A

    公开(公告)日：2000-03-21

    申请号：US23166

    申请日：1998-02-13

    申请人： Unsoon Kim ,  Yowjuang W. Liu ,  Yu Sun

    发明人： Unsoon Kim ,  Yowjuang W. Liu ,  Yu Sun

    IPC分类号： H01L21/762 ,  H01L29/788

    CPC分类号： H01L21/76232 ,  H01L21/76237

    摘要： A wet etching process for establishing isolation grooves in a flash memory core wafer includes depositing nitride and/or oxide layers on a silicon substrate of the wafer, depositing a photoresist layer thereon, and then exposing predetermined portions of the photoresist layer to ultraviolet light to establish a desired groove pattern in the photoresist layer. A dry etching process is then used to remove the nitride and/or oxide layers beneath the groove pattern of the photoresist layer to thereby expose portions of the substrate. Next, the wafer is disposed in a wet etching solution such as potassium hydroxide to form grooves in the exposed portions of the silicon substrate. The wafer is oriented and disposed in the bath as appropriate for forming V-shaped grooves, such that after etching, the angled walls of the grooves can be easily exposed to a dopant beam directly above the wafer, without having to tilt the wafer or beam source. Thereby, the walls of the grooves are easily implanted with dopant.

    摘要翻译： 用于在闪速存储器芯晶片中建立隔离槽的湿蚀刻工艺包括在晶片的硅衬底上沉积氮化物和/或氧化物层，在其上沉积光致抗蚀剂层，然后将光致抗蚀剂层的预定部分暴露于紫外光以建立 在光致抗蚀剂层中的期望的凹槽图案。 然后使用干蚀刻工艺去除光致抗蚀剂层的凹槽图案下方的氮化物和/或氧化物层，从而暴露衬底的部分。 接下来，将晶片设置在诸如氢氧化钾的湿蚀刻溶液中，以在硅衬底的暴露部分中形成凹槽。 晶片被定向并适当地设置在浴中以形成V形槽，使得在蚀刻之后，槽的成角度的壁可以容易地暴露于直接在晶片上方的掺杂剂束，而不必使晶片或光束倾斜 资源。 因此，槽的壁容易用掺杂剂注入。

    Memory device having improved periphery and core isolation
    9.
    发明授权
    Memory device having improved periphery and core isolation 失效
    具有改进的外围和核心隔离的存储器件

    公开(公告)号：US07078314B1

    公开(公告)日：2006-07-18

    申请号：US10407999

    申请日：2003-04-03

    申请人： Unsoon Kim ,  Hiroyuki Kinoshita ,  Yu Sun

    发明人： Unsoon Kim ,  Hiroyuki Kinoshita ,  Yu Sun

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76229 ,  H01L27/105 ,  H01L27/1052

    摘要： The present invention discloses a memory device having an improved periphery isolation region and core isolation region. A first trench is formed in a core region. Substrate material bordering the first trench is then oxidized to form a first liner. The first liner is then removed. A second trench is then formed in a periphery region. A second oxidation is then performed such that a second liner is formed from the substrate material bordering the first and second trenches. A dielectric trench fill having substantially uniform density is then deposited in the first and second trenches.

    摘要翻译： 本发明公开了一种具有改进的外围隔离区域和核心隔离区域的存储器件。 第一沟槽形成在芯区域中。 然后与第一沟槽接壤的衬底材料被氧化以形成第一衬里。 然后将第一个衬垫取出。 然后在周边区域中形成第二沟槽。 然后执行第二氧化，使得第二衬垫由与第一和第二沟槽接壤的衬底材料形成。 然后在第一和第二沟槽中沉积具有基本均匀密度的电介质沟槽填料。

    Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space
    10.
    发明授权
    Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space 有权
    非自对准浅沟槽隔离工艺与一次性空间定义亚光刻多孔空间

    公开(公告)号：US06664191B1

    公开(公告)日：2003-12-16

    申请号：US09973131

    申请日：2001-10-09

    申请人： Unsoon Kim ,  Yider Wu ,  Yu Sun ,  Michael K. Templeton ,  Angela T. Hui ,  Chi Chang

    发明人： Unsoon Kim ,  Yider Wu ,  Yu Sun ,  Michael K. Templeton ,  Angela T. Hui ,  Chi Chang

    IPC分类号： H01L21302

    CPC分类号： H01L27/11526 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76229 ,  H01L21/76838 ,  H01L27/11531 ,  Y10S438/975

    摘要： A method is provided of forming lines with spaces between memory cells below a minimum printing dimension of a photolithographic tool set. In one aspect of the invention, lines and spaces are formed in a first polysilicon layer that forms floating gates of flash memory cells. STI regions are formed between adjacent memory cells in a substrate to isolate the cells from one another. The first polysilicon layer is deposited over the substrate covering the STI regions. The first polysilicon layer is then planarized by a CMP process or the like to eliminate overlay issues associated with the STI regions. A hard mask layer is deposited over the first polysilicon layer and a first space dimension d1 etched between adjacent memory cells. A conformal nitride layer is deposited over the hard mask layer and an etch step performed to form nitride side walls adjacent the spaces. The nitride side walls reduce the first space dimension to a second space dimension d2, so that spaces can be formed in the first polysilicon layer at a dimension smaller than the minimum printable dimension of the photolithographic tool set.

    摘要翻译： 提供了一种在光刻工具组的最小打印尺寸之下形成具有在存储器单元之间的空间的线的方法。 在本发明的一个方面，线和间隔形成在形成闪存单元的浮动栅极的第一多晶硅层中。 STI区域形成在衬底中的相邻存储单元之间，以隔离细胞。 第一多晶硅层沉积在覆盖STI区域的衬底上。 然后通过CMP工艺等将第一多晶硅层平坦化，以消除与STI区域相关联的覆盖问题。 在第一多晶硅层上沉积硬掩模层，并在相邻的存储单元之间蚀刻第一空间尺寸d1。 在硬掩模层上沉积共形氮化物层，并且执行蚀刻步骤以形成邻近空间的氮化物侧壁。 氮化物侧壁将第一空间尺寸减小到第二空间尺寸d2，使得可以以小于光刻工具组的最小可打印尺寸的尺寸在第一多晶硅层中形成空间。