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    Semiconductor device and semiconductor integrated circuit having a conductive film on element region
    1.
    发明授权
    Semiconductor device and semiconductor integrated circuit having a conductive film on element region 失效
    在元件区域上具有导电膜的半导体器件和半导体集成电路

    公开(公告)号：US06396086B1

    公开(公告)日：2002-05-28

    申请号：US09404090

    申请日：1999-09-23

    申请人： Yuji Takeuchi ,  Riichiro Shirota ,  Seiichi Aritome ,  Masashi Umemura ,  Yuuichiro Murahama ,  Hitoshi Araki ,  Masamitsu Yahata ,  Osamu Ikeda

    发明人： Yuji Takeuchi ,  Riichiro Shirota ,  Seiichi Aritome ,  Masashi Umemura ,  Yuuichiro Murahama ,  Hitoshi Araki ,  Masamitsu Yahata ,  Osamu Ikeda

    IPC分类号： H01L2710

    CPC分类号： H01L27/088 ,  H01L21/76838 ,  H01L27/0629 ,  H01L27/0805 ,  H01L29/94

    摘要： In a semiconductor device of MOS structure, the element region has a shape such as a square shape which has a plurality of sides and a plurality of corners. On the element region, a conductive film which constitutes one electrode of the MOS structure is formed. The other electrode of the MOS structure is a silicon substrate. The conductive film is provided so as to cover at least sides adjacent to each other and so as not to cover the corners including the corners which are the contact points (intersecting points) of the adjacent sides. Further, in case the element region is in a ring shape, the conductive film is provided so as to cover none of the corners including the inside corners of the ring-shaped element region. By the above-mentioned structure, the occurrence of breakdown in the insulation film in the MOS structure can be prevented, and the reliability thereof can be enhanced.

    摘要翻译： 在MOS结构的半导体器件中，元件区域具有多个侧面和多个角的方形的形状。 在元件区域上形成构成MOS结构的一个电极的导电膜。 MOS结构的另一个电极是硅衬底。 导电膜被设置成覆盖彼此相邻的至少边，并且不覆盖包括作为相邻侧的接触点（交叉点）的角部的角部。 此外，在元件区域为环形的情况下，导电膜被设置成不覆盖包括环形元件区域的内角的任何角。 通过上述结构，可以防止在MOS结构中的绝缘膜中发生击穿，从而可以提高其可靠性。

    Semiconductor device
    2.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US06611010B2

    公开(公告)日：2003-08-26

    申请号：US09726582

    申请日：2000-12-01

    申请人： Akira Goda ,  Kazuhiro Shimizu ,  Yuji Takeuchi ,  Riichiro Shirota ,  Seiichi Aritome

    发明人： Akira Goda ,  Kazuhiro Shimizu ,  Yuji Takeuchi ,  Riichiro Shirota ,  Seiichi Aritome

    IPC分类号： H01L2710

    CPC分类号： H01L21/76877 ,  H01L21/76885 ,  H01L23/5226 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a bit line contact section, a contact hole is formed through a silicon oxide film, and a contact plug made of a polysilicon film doped with impurities is buried in the contact hole. The silicon oxide film is formed with a wiring groove overlapping the contact hole. A bit line made of a metal film is buried in the wiring groove. The contact plug extends through the bit line, and has its upper surface substantially coplanar with an upper surface of the bit line. The contact plug is in contact with the bit line only on its side surfaces.

    摘要翻译： 在位线接触部分中，通过氧化硅膜形成接触孔，并且在接触孔中埋设由掺杂杂质的多晶硅膜制成的接触塞。 氧化硅膜形成有与接触孔重叠的布线槽。 由金属膜制成的位线埋在布线槽中。 接触插塞延伸穿过位线，并且其上表面与位线的上表面基本上共面。 接触插塞仅在其侧面与位线接触。

    Semiconductor device and method of fabricating the same
    5.
    发明授权
    Semiconductor device and method of fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US06680230B2

    公开(公告)日：2004-01-20

    申请号：US10201111

    申请日：2002-07-24

    申请人： Norihisa Arai ,  Fumitaka Arai ,  Seiichi Aritome ,  Akira Shimizu ,  Riichiro Shirota

    发明人： Norihisa Arai ,  Fumitaka Arai ,  Seiichi Aritome ,  Akira Shimizu ,  Riichiro Shirota

    IPC分类号： H01L21336

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546

    摘要： A method of fabricating a semiconductor device which has a cell array with non-volatile memory transistors and a peripheral circuit including a first transistor and a second transistor as driven by a lower voltage than the first transistor is disclosed. The method includes the steps of forming over a semiconductor substrate a first gate dielectric film for use in the first transistor, selectively etching the first gate dielectric film in the cell array region to expose the substrate, forming over the exposed substrate a second gate dielectric film which is for use as a tunnel dielectric film of the memory transistors, forming a first gate electrode material film over the first and second gate dielectric films, selectively etching the first gate electrode material film and its underlying first gate dielectric film in the second transistor region, forming over the exposed substrate a third gate dielectric film which is for use in the second transistor, forming a second gate electrode material film over the third gate dielectric film, and forming gates of the respective transistors while letting the gates at least partly include the first and second gate electrode material films.

    摘要翻译： 公开了一种制造半导体器件的方法，该半导体器件具有具有非易失性存储晶体管的单元阵列和包括由比第一晶体管低的电压驱动的第一晶体管和第二晶体管的外围电路。 该方法包括以下步骤：在半导体衬底上形成用于第一晶体管的第一栅极电介质膜，选择性地蚀刻电池阵列区域中的第一栅极电介质膜以暴露衬底，在暴露的衬底上形成第二栅极电介质膜 其用作存储晶体管的隧道电介质膜，在第一和第二栅极电介质膜上形成第一栅电极材料膜，在第二晶体管区域中选择性地蚀刻第一栅电极材料膜及其下面的第一栅极电介质膜 在暴露的衬底上形成用于第二晶体管的第三栅极电介质膜，在第三栅极电介质膜上形成第二栅电极材料膜，并且在使栅极至少部分地包括 第一和第二栅电极材料膜。

    Non-volatile semiconductor memory device with nand type memory cell arrays
    7.
    发明授权
    Non-volatile semiconductor memory device with nand type memory cell arrays 失效
    具有n型存储单元阵列的非易失性半导体存储器件

    公开(公告)号：US5978265A

    公开(公告)日：1999-11-02

    申请号：US746176

    申请日：1991-08-15

    申请人： Ryouhei Kirisawa ,  Riichiro Shirota ,  Ryozo Nakayama ,  Seiichi Aritome ,  Masaki Momodomi ,  Yasuo Itoh ,  Fujio Masuoka

    发明人： Ryouhei Kirisawa ,  Riichiro Shirota ,  Ryozo Nakayama ,  Seiichi Aritome ,  Masaki Momodomi ,  Yasuo Itoh ,  Fujio Masuoka

    IPC分类号： G11C17/12 ,  G11C16/04 ,  G11C16/10 ,  G11C17/00 ,  G11C11/34

    CPC分类号： G11C16/0483 ,  G11C16/10

    摘要： An electrically erasable programmable read-only memory is disclosed which has programmable memory cells connected to parallel bit lines provided above a semiconductor substrate. The memory cells include NAND cell blocks each of which has a series array of memory cell transistors. Parallel word lines are connected to the control gates of the memory cell transistors, respectively. In a data write mode, a selection transistor in a certain NAND cell block including a selected memory cell is rendered conductive to connect the certain cell block to a corresponding bit line associated therewith. Under such a condition, electrons are tunnel-injected into a floating gate of the selected memory cell transistor, and the threshold value of the certain transistor is increased to be a positive value. A logical data is thus written in the selected memory cell transistor. The data in the selected cell transistor is erased by discharging carriers accumulated in the floating gate thereof to its drain or the substrate, so that the threshold value of the certain transistor is decreased to be a negative value.

    摘要翻译： 公开了一种电可擦除可编程只读存储器，其具有连接到设置在半导体衬底上的并行位线的可编程存储器单元。 存储单元包括NAND单元块，每个NAND单元具有存储单元晶体管的串联阵列。 并行字线分别连接到存储单元晶体管的控制栅极。 在数据写入模式中，包括所选择的存储单元的某个NAND单元块中的选择晶体管被导通以将特定单元块连接到与其相关联的相应位线。 在这种条件下，电子被隧道注入到所选择的存储单元晶体管的浮动栅极中，并且特定晶体管的阈值增加到正值。 因此，逻辑数据被写入所选择的存储单元晶体管中。 通过将其浮置栅极中累积的载流子放电到其漏极或衬底来擦除所选择的单元晶体管中的数据，使得某个晶体管的阈值降低为负值。