公开(公告)号：US08324960B2

公开(公告)日：2012-12-04

申请号：US12849503

申请日：2010-08-03

Applicant: Ming-Chieh Huang ,  Chan-Hong Chern ,  Chih-Chang Lin ,  Tien-Chun Yang ,  Yuwen Swei

Inventor： Ming-Chieh Huang ,  Chan-Hong Chern ,  Chih-Chang Lin ,  Tien-Chun Yang ,  Yuwen Swei

IPC: G05F1/10 ,  G05F3/02

CPC classification number: H02M3/07

Abstract: An integrated circuit includes a first PMOS transistor, where its drain is arranged to be coupled to a voltage output, and its source is coupled to the drain of a second PMOS transistor. The source of the second PMOS transistor is arranged to be coupled to a high power supply voltage. The source and drain of a MOS capacitor are coupled to the source of the first PMOS transistor. The drain of an NMOS transistor is coupled to the drain of the first PMOS transistor. The integrated circuit is configured to receive a voltage input to generate the voltage output having a maximum voltage higher than the voltage input. The gate oxide layer thickness of the MOS capacitor is less than that of the first PMOS transistor.

Abstract translation: 集成电路包括第一PMOS晶体管，其中其漏极被布置成耦合到电压输出，并且其源极耦合到第二PMOS晶体管的漏极。 第二PMOS晶体管的源极被布置成耦合到高电源电压。 MOS电容器的源极和漏极耦合到第一PMOS晶体管的源极。 NMOS晶体管的漏极耦合到第一PMOS晶体管的漏极。 集成电路被配置为接收电压输入以产生具有高于电压输入的最大电压的电压输出。 MOS电容器的栅氧化层厚度小于第一PMOS晶体管的栅极氧化层厚度。

公开(公告)号：US20120266126A1

公开(公告)日：2012-10-18

申请号：US13084748

申请日：2011-04-12

Applicant: Chan-Hong CHERN ,  Fu-Lung HSUEH ,  Li-Chun TIEN

Inventor： Chan-Hong CHERN ,  Fu-Lung HSUEH ,  Li-Chun TIEN

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A method of designing an integrated circuit includes providing a cell library including a first and second cell structures. The cell structures each include a dummy gate electrode disposed on a boundary. An edge gate electrode is disposed adjacent to the dummy gate electrode. An oxide definition (OD) region has an edge disposed between the edge gate electrode and the dummy gate electrode. The method includes determining if the cell structures are to be abutted with each other. If so, the method includes abutting the cell structures. If not so, the method includes increasing areas of portions of the OD regions between the edge gate electrodes and the dummy gate electrodes.

Abstract translation: 设计集成电路的方法包括提供包括第一和第二单元结构的单元库。 电池结构各自包括设置在边界上的虚拟栅电极。 边缘栅电极被设置成与虚拟栅电极相邻。 氧化物定义（OD）区域具有设置在边缘栅电极和伪栅电极之间的边缘。 该方法包括确定单元结构是否彼此邻接。 如果是，则该方法包括邻接单元结构。 如果不是这样，则该方法包括增加边缘栅极电极和虚拟栅电极之间的OD区域的部分区域。

公开(公告)号：US08217729B2

公开(公告)日：2012-07-10

申请号：US12706825

申请日：2010-02-17

Applicant: Chan-Hong Chern ,  Fu-Lung Hsueh ,  Chiang Pu ,  Chih-Chang Lin

Inventor： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Chiang Pu ,  Chih-Chang Lin

IPC: H03B5/08

CPC classification number: H03L5/00 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03L7/099

Abstract: An integrated circuit includes an inductor-capacitor (LC) tank circuit coupled with a feedback loop. The LC tank circuit is configured to output an output signal having a peak voltage that is substantially equal to a direct current (DC) voltage level plus an amplitude. The feedback loop is capable of determining if the peak voltage of the output signal falls within a range between a first voltage level and a second voltage level for adjusting the amplitude of the output signal.

Abstract translation: 集成电路包括与反馈回路耦合的电感器 - 电容（LC）电路。 LC槽电路被配置为输出具有基本上等于直流（DC）电压电平加上幅度的峰值电压的输出信号。 反馈回路能够确定输出信号的峰值电压是否落在用于调节输出信号的幅度的第一电压电平和第二电压电平之间的范围内。

公开(公告)号：US20120032518A1

公开(公告)日：2012-02-09

申请号：US12851023

申请日：2010-08-05

Applicant: Ming-Chieh HUANG ,  Chan-Hong CHERN ,  David Barry SCOTT

Inventor： Ming-Chieh HUANG ,  Chan-Hong CHERN ,  David Barry SCOTT

IPC: H02J1/10

CPC classification number: H02J7/35 ,  H02J1/10 ,  H02J7/0055 ,  H02J7/025 ,  H02J17/00 ,  H02J50/00 ,  H02J50/20 ,  H02J50/30 ,  H02J50/40 ,  Y10T307/702

Abstract: An energy harvesting system includes a plurality of transducers. The transducers are configured to generate direct current (DC) voltages from a plurality of ambient energy sources. A sensor control circuit has a plurality of sensors configured to detect the DC signals from the plurality of transducers. A DC-to-DC converter is configured to supply an output voltage. A plurality of switches, each switch coupled between the DC-to-DC converter and a corresponding transducer of the plurality of transducers. The sensor control circuit enables one switch of the plurality of switches and disables the other switches of the plurality of switches based on a priority criterion.

Abstract translation: 能量收集系统包括多个换能器。 传感器被配置为从多个环境能量源产生直流（DC）电压。 传感器控制电路具有被配置为检测来自多个换能器的直流信号的多个传感器。 DC-DC转换器被配置为提供输出电压。 多个开关，每个开关耦合在DC-DC转换器和多个换能器中的相应换能器之间。 传感器控制电路使得多个开关中的一个开关能够基于优先级标准而禁用多个开关中的其它开关。

公开(公告)号：US20120019302A1

公开(公告)日：2012-01-26

申请号：US12843479

申请日：2010-07-26

Applicant: Chan-Hong CHERN ,  Fu-Lung HSUEH ,  Ming-Chieh HUANG ,  Chih-Chang LIN

Inventor： Chan-Hong CHERN ,  Fu-Lung HSUEH ,  Ming-Chieh HUANG ,  Chih-Chang LIN

IPC: H03L5/00

CPC classification number: H03K19/018521

Abstract: A level shifter includes one PMOS and two NMOS transistors. A source of the first NMOS transistor is coupled to a low power supply voltage. An input signal is coupled to a gate of the first NMOS transistor and a source of the second NMOS transistor. The input signal has a voltage level up to a first power supply voltage. A source of the PMOS transistor is coupled to a second power supply voltage, higher than the first power supply voltage. An output signal is coupled between the PMOS and the first NMOS transistors. The first NMOS transistor is arranged to pull down the output signal when the input signal is a logical 1, and the second NMOS transistor is arranged to enable the PMOS transistor to pull up the output signal to a logical 1 at the second power supply voltage when the input signal is a logical 0.

Abstract translation: 电平移位器包括一个PMOS和两个NMOS晶体管。 第一NMOS晶体管的源极耦合到低电源电压。 输入信号耦合到第一NMOS晶体管的栅极和第二NMOS晶体管的源极。 输入信号具有高达第一电源电压的电压电平。 PMOS晶体管的源极耦合到高于第一电源电压的第二电源电压。 输出信号耦合在PMOS和第一NMOS晶体管之间。 第一NMOS晶体管被布置为当输入信号为逻辑1时下拉输出信号，并且第二NMOS晶体管被布置为使得PMOS晶体管能够以第二电源电压将输出信号上拉至逻辑1， 输入信号为逻辑0。

公开(公告)号：US08004354B1

公开(公告)日：2011-08-23

申请号：US12704719

申请日：2010-02-12

Applicant: Chiang Pu ,  Ming-Chich Huang ,  Chan-Hong Chern ,  Tien-Chun Yang

Inventor： Chiang Pu ,  Ming-Chich Huang ,  Chan-Hong Chern ,  Tien-Chun Yang

IPC: H03F1/36

CPC classification number: G01C19/5776

Abstract: Some embodiments regard a circuit comprising: a high voltage transistor providing a resistance; an amplifier configured to receive a current and to convert the current to a first voltage that is used in a loop creating the current; and an automatic level control circuit that, based on an AC amplitude of the first voltage, adjusts a second voltage at a gate of the high voltage transistor and thereby adjusts the resistance and the first voltage; wherein the automatic level control circuit is configured to adjust the first voltage toward the first reference voltage if the first voltage differs from a first reference voltage.

Abstract translation: 一些实施例涉及一种电路，包括：提供电阻的高压晶体管; 放大器，被配置为接收电流并将电流转换成在产生电流的环路中使用的第一电压; 以及自动电平控制电路，其基于所述第一电压的交流振幅调整所述高电压晶体管的栅极处的第二电压，从而调整所述电阻和所述第一电压; 其中所述自动电平控制电路被配置为如果所述第一电压与第一参考电压不同，则将所述第一电压调整为朝向所述第一参考电压。

公开(公告)号：US20110199063A1

公开(公告)日：2011-08-18

申请号：US12706825

申请日：2010-02-17

Applicant: Chan-Hong Chern ,  Fu-Lung Hsueh ,  Chiang Pu ,  Chih-Chang Lin

Inventor： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Chiang Pu ,  Chih-Chang Lin

IPC: G05F1/10

CPC classification number: H03L5/00 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03L7/099

Abstract: An integrated circuit includes an inductor-capacitor (LC) tank circuit coupled with a feedback loop. The LC tank circuit is configured to output an output signal having a peak voltage that is substantially equal to a direct current (DC) voltage level plus an amplitude. The feedback loop is capable of determining if the peak voltage of the output signal falls within a range between a first voltage level and a second voltage level for adjusting the amplitude of the output signal.

Abstract translation: 集成电路包括与反馈回路耦合的电感器 - 电容（LC）电路。 LC槽电路被配置为输出具有基本上等于直流（DC）电压电平加上幅度的峰值电压的输出信号。 反馈回路能够确定输出信号的峰值电压是否落在用于调节输出信号的幅度的第一电压电平和第二电压电平之间的范围内。

公开(公告)号：US06326664B1

公开(公告)日：2001-12-04

申请号：US08971992

申请日：1997-11-17

Applicant: Robert S. Chau ,  Chan-Hong Chern ,  Chia-Hong Jan ,  Kevin R. Weldon ,  Paul A. Packan ,  Leopoldo D. Yau

Inventor： Robert S. Chau ,  Chan-Hong Chern ,  Chia-Hong Jan ,  Kevin R. Weldon ,  Paul A. Packan ,  Leopoldo D. Yau

IPC: H01L2906

CPC classification number: H01L29/0847 ,  H01L21/2254 ,  H01L21/2257 ,  H01L21/2807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66613 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: A novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip comprising an ultra shallow region which extends beneath the gate electrode and a raised region.

Abstract translation: 具有低电阻超浅尖端区域的新型晶体管及其制造方法。 本发明的新型晶体管具有源极/漏极延伸部分或尖端，其包括在栅电极下方延伸的超浅区域和升高的区域。

公开(公告)号：US5891809A

公开(公告)日：1999-04-06

申请号：US536653

申请日：1995-09-29

Applicant: Robert S. K. Chau ,  Lawrence N. Brigham ,  Chia-Hong Jan ,  Chan-Hong Chern ,  Binny P. Arcot

Inventor： Robert S. K. Chau ,  Lawrence N. Brigham ,  Chia-Hong Jan ,  Chan-Hong Chern ,  Binny P. Arcot

IPC: H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  H01L21/336 ,  H01L21/762 ,  H01L29/51 ,  H01L21/31

CPC classification number: H01L21/28185 ,  H01L21/0214 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/3144 ,  H01L21/31662 ,  H01L21/76235 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/6659

Abstract: A method of forming a thin, robust nitrided oxide layer. The process results in a manufacturable, uniform, low-defect density, reliable nitrided oxide that may be used as a gate dielectric, as a portion of a spacer, or as a portion of a trench isolation. First, a substrate is oxidized in a chlorinated dry oxidation followed by a low temperature pyrogenic steam oxidation. Next, a low temperature ammonia anneal is performed, followed by a high temperature anneal in an inert ambient.

Abstract translation: 形成薄而坚固的氮化氧化物层的方法。 该方法产生可制造，均匀，低缺陷密度，可靠的氮化氧化物，其可以用作栅极电介质，作为间隔物的一部分，或者作为沟槽隔离的一部分。 首先，将基板在氯化干燥氧化中氧化，然后进行低温热解蒸汽氧化。 接下来，进行低温氨退火，随后在惰性环境中进行高温退火。

公开(公告)号：US5856697A

公开(公告)日：1999-01-05

申请号：US895270

申请日：1997-07-14

Applicant: Stephen Chambers ,  Brian J. Brown ,  Chan-Hong Chern ,  Robert Chau ,  Leopoldo D. Yau

Inventor： Stephen Chambers ,  Brian J. Brown ,  Chan-Hong Chern ,  Robert Chau ,  Leopoldo D. Yau

IPC: H01L21/331 ,  H01L21/8249 ,  H01L29/08 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L29/66272 ,  H01L21/8249 ,  H01L29/0804 ,  Y10S148/01 ,  Y10S148/011

Abstract: A new method of isolating a polysilicon emitter from the base region of a bipolar transistor, trenching the polysilicon emitter into the semiconductor substrate, and maintaining a consistent base width of a bipolar transistor independent of variations in emitter mask thicknesses is disclosed. The polysilicon emitter isolation provides for better electrical breakdown characteristics between the emitter and the base by protecting the dielectric layer between the polysilicon emitter and base regions from defects and contamination associated with the BiCMOS manufacturing environment. The polysilicon emitter is trenched into the semiconductor substrate in order to reduce transistor operation problems associated with hot electron injection. Consistent base widths improve transistor performance uniformity thereby improving manufacturability and reliability.

Abstract translation: 公开了一种从双极晶体管的基极区域隔离多晶硅发射极的新方法，将多晶硅发射极沟槽到半导体衬底中，并保持独立于发射极掩模厚度变化的双极晶体管的一致的基底宽度。 多晶硅发射极隔离通过保护多晶硅发射极和基极区域之间的电介质层与BiCMOS制造环境相关的缺陷和污染来提供发射极和基极之间的更好的电击穿特性。 为了减少与热电子注入相关的晶体管操作问题，多晶硅发射极被沟入半导体衬底。 一致的基极宽度提高了晶体管的性能均匀性，从而提高了可制造性和可靠性。