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    GATE ISOLATION FOR MULTIGATE DEVICE
    91.
    发明公开
    GATE ISOLATION FOR MULTIGATE DEVICE 审中-公开

    公开(公告)号：US20240312987A1

    公开(公告)日：2024-09-19

    申请号：US18668911

    申请日：2024-05-20

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Kuo-Cheng Chiang ,  Shi Ning Ju ,  Guan-Lin Chen ,  Kuan-Ting Pan ,  Chih-Hao Wang

    IPC分类号： H01L27/088 ,  H01L21/762 ,  H01L29/423 ,  H01L29/786

    CPC分类号： H01L27/088 ,  H01L21/76224 ,  H01L29/42392 ,  H01L29/78696

    摘要： Gate cutting techniques disclosed herein form gate isolation fins to isolate metal gates of multigate devices from one another before forming the multigate devices, and in particular, before forming the metal gates of the multigate devices. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A gate isolation fin, which separates the first metal gate and the second metal gate, includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is less than the first dielectric constant. A gate isolation end cap may be disposed on the gate isolation fin to provide additional isolation.

    Fin Isolation Regions With Improved Depth Distribution and Methods Forming the Same
    92.
    发明公开
    Fin Isolation Regions With Improved Depth Distribution and Methods Forming the Same 审中-公开

    公开(公告)号：US20240312843A1

    公开(公告)日：2024-09-19

    申请号：US18184024

    申请日：2023-03-15

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Tzu-Ging Lin ,  Yi-Chun Chen ,  Jih-Jse Lin

    IPC分类号： H01L21/8234 ,  H01L27/088

    CPC分类号： H01L21/823481 ,  H01L21/823431 ,  H01L27/0886

    摘要： A method includes forming a gate stack on a semiconductor region, wherein the semiconductor region is over a bulk semiconductor substrate. The gate stack is etched to form a first trench, wherein a plurality of protruding semiconductor fins are revealed to the first trench. The plurality of protruding semiconductor fins are etched to form a plurality of second trenches extending into the bulk semiconductor substrate. The plurality of second trenches are underlying and joined to the first trench. The plurality of second trenches include a first outmost trench having a first depth, a second outmost trench, and an inner trench between the first outmost trench and the second outmost trench. The inner trench has a second depth equal to or smaller than the first depth. A fin isolation region is formed to fill the first trench and the plurality of second trenches.

    SUBSTRATE HOLDER AND METHODS OF USE
    98.
    发明公开
    SUBSTRATE HOLDER AND METHODS OF USE 审中-公开

    公开(公告)号：US20240304488A1

    公开(公告)日：2024-09-12

    申请号：US18665134

    申请日：2024-05-15

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Yu-Chi TSAI ,  Chueh-Chi KUO

    IPC分类号： H01L21/683 ,  G03F7/00 ,  G03F7/20

    CPC分类号： H01L21/6833 ,  G03F7/2041 ,  G03F7/70708

    摘要： An electrostatic substrate holder for use in an extreme ultraviolet radiation lithography system includes a substrate receiving surface having a plurality of gas passages in fluid communication with a variable gas pressure pump. Varying the pressure in a void space between the backside of the substrate and the substrate receiving surface of the substrate holder promotes removal of non-gaseous materials within the void space between the backside of the substrate and the substrate receiving surface of the substrate holder.