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    Power and temperature driven clock throttling
    91.
    发明授权
    Power and temperature driven clock throttling 有权

    公开(公告)号：US11709522B1

    公开(公告)日：2023-07-25

    申请号：US17023016

    申请日：2020-09-16

    Applicant: XILINX, INC.

    Inventor： Sebastian Turullols ,  Ravinder Sharma ,  Siva Santosh Kumar Pyla ,  Raj Kumar Rampelli ,  Deboleena Minz Sakalley ,  Nilay Shah

    IPC: G06F1/26 ,  G06F1/08

    CPC classification number: G06F1/08 ,  G06F1/26

    Abstract: Embodiments herein describe techniques for managing power consumption and temperature in an electronic circuits or integrated chips driven by clock signals (collectively referred to as “cards”) by throttling the clock signals on those cards. The cards often allow users to implement customized hardware acceleration functions via Field Programmable Gate Arrays or the like, which can lead to variable workloads on different cards (or regions of individual cards) based on the customized functionality. By throttling the clock signal based on continuously monitored power consumption or temperature, the user is enabled to use the card more aggressively (e.g., based on average rather than worst-case power consumption), and the card automatically throttles operations when power consumption or temperature exceeds operational thresholds.

    TRANSPARENT AND REMOTE KERNEL EXECUTION IN A HETEROGENEOUS COMPUTING SYSTEM
    92.
    发明公开
    TRANSPARENT AND REMOTE KERNEL EXECUTION IN A HETEROGENEOUS COMPUTING SYSTEM 审中-公开

    公开(公告)号：US20230229497A1

    公开(公告)日：2023-07-20

    申请号：US17648172

    申请日：2022-01-17

    Applicant: Xilinx, Inc.

    Inventor： Sonal Santan ,  Yu Liu ,  Yenpang Lin ,  Stephen P. Rozum

    IPC: G06F9/50 ,  G06F9/54 ,  G06F9/30 ,  G06F12/02

    CPC classification number: G06F9/5016 ,  G06F9/544 ,  G06F9/30043 ,  G06F12/0238 ,  G06F2212/7201

    Abstract: Remote kernel execution in a heterogeneous computing system can include executing, using a device processor of a device communicatively linked to a host processor, a device runtime and receiving from the host processor within a hardware submission queue of the device, a command. The command requests execution of a software kernel and specifies a descriptor stored in a region of a memory of the device shared with the host processor. In response to receiving the command, the device runtime, as executed by the device processor, invokes a runner program associated with the software kernel. The runner program can map a physical address of the descriptor to a virtual memory address corresponding to the descriptor that is usable by the software kernel. The runner program can execute the software kernel. The software kernel can access data specified by the descriptor using the virtual memory address as provided by the runner program.

    PARITY PROTECTION OF CONTROL REGISTERS
    93.
    发明公开
    PARITY PROTECTION OF CONTROL REGISTERS 审中-公开

    公开(公告)号：US20230222026A1

    公开(公告)日：2023-07-13

    申请号：US17574340

    申请日：2022-01-12

    Applicant: XILINX, INC.

    Inventor： Sarosh I. AZAD ,  Aditi R. GANESAN

    IPC: G06F11/07 ,  G06F11/10

    CPC classification number: G06F11/0751 ,  G06F11/1004 ,  G06F11/0772

    Abstract: An integrated circuit (IC) device for detecting errors within a register, the IC device includes registers and parity checking circuitry. The parity checking circuitry is coupled to the registers and comprises a first parity circuitry, a second parity circuit, and error detection circuitry. The first parity circuit receives first register values from the registers and determine a first value from the first register values. The second parity circuit is receives second register values from the registers and determines a second value from the second register values. The error detection circuitry compares the first value and the second value to detect a first error within the registers, and output an error signal indicating the first error.

    Core cavity noise isolation structure for use in chip packages
    96.
    发明授权
    Core cavity noise isolation structure for use in chip packages 有权

    公开(公告)号：US11688675B1

    公开(公告)日：2023-06-27

    申请号：US17315229

    申请日：2021-05-07

    Applicant: XILINX, INC.

    Inventor： Frank Peter Lambrecht ,  Po-Wei Chiu ,  Hong Shi

    IPC: H01L23/498 ,  H01L21/48 ,  H01L23/552

    CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/552

    Abstract: Various noise isolation structures and methods for fabricating the same are presented. In one example, a substrate for chip package is provided. The substrate includes a core region, top build-up layers and bottom build-up layers. The top build-up layers are formed on a first side of the core region and the bottom build-up layers are formed on a second side of the core region that is opposite the first side. Routing circuitry formed in the bottom build-up layers is coupled to routing circuitry formed in the top build-up layers by vias formed through the core region. A void is formed in the bottom build-up layers. The void is configured as a noise isolation structure. The void has a sectional area that is different in at least two different distances from the core region.

    BREAKOUT STRUCTURE FOR AN INTEGRATED CIRCUIT DEVICE
    97.
    发明公开
    BREAKOUT STRUCTURE FOR AN INTEGRATED CIRCUIT DEVICE 审中-公开

    公开(公告)号：US20230199941A1

    公开(公告)日：2023-06-22

    申请号：US17557877

    申请日：2021-12-21

    Applicant: XILINX, INC.

    Inventor： Shad SHEPSTON ,  Robert Andrew DANIELS

    IPC: H05K1/02 ,  H05K1/11

    CPC classification number: H05K1/0228 ,  H05K1/114 ,  H05K1/0219 ,  H05K1/181

    Abstract: Apparatus having at least one breakout structure are provided. In one example, an apparatus includes a dielectric layer, first and second contact pads, and first and second vias. The first and second contact pads are disposed on the dielectric layer. The first via is disposed through the dielectric layer and coupled to the first contact pad. The first via is offset from the first contact pad in a first direction. The second contact pad is immediately adjacent the first via. The second via is disposed through the dielectric layer immediately adjacent the first contact pad and coupled to the second contact pad. The second via is offset from the second contact pad in a second direction that is opposite of the first direction. The first and the second contact pads define a first differential pair of contact pads that is configured to transmit a first differential pair of signals.

    MACHINE LEARNING MODEL UPDATES TO ML ACCELERATORS
    98.
    发明公开
    MACHINE LEARNING MODEL UPDATES TO ML ACCELERATORS 审中-公开

    公开(公告)号：US20230195684A1

    公开(公告)日：2023-06-22

    申请号：US18112362

    申请日：2023-02-21

    Applicant: XILINX, INC.

    Inventor： Jaideep DASTIDAR ,  Millind MITTAL

    IPC: G06F15/78 ,  G06N20/00 ,  G06F9/54 ,  G06F13/42 ,  H04L12/66 ,  G06F3/06

    CPC classification number: G06F15/7825 ,  G06N20/00 ,  G06F9/544 ,  G06F9/546 ,  G06F13/4282 ,  H04L12/66 ,  G06F3/067 ,  G06F2213/0026

    Abstract: Examples herein describe a peripheral I/O device with a hybrid gateway that permits the device to have both I/O and coherent domains. As a result, the compute resources in the coherent domain of the peripheral I/O device can communicate with the host in a similar manner as CPU-to-CPU communication in the host. The dual domains in the peripheral I/O device can be leveraged for machine learning (ML) applications. While an I/O device can be used as an ML accelerator, these accelerators previously only used an I/O domain. In the embodiments herein, compute resources can be split between the I/O domain and the coherent domain where a ML engine is in the I/O domain and a ML model is in the coherent domain. An advantage of doing so is that the ML model can be coherently updated using a reference ML model stored in the host.

    MULTI-PHASE CLOCK SIGNAL GENERATION CIRCUITRY
    100.
    发明公开
    MULTI-PHASE CLOCK SIGNAL GENERATION CIRCUITRY 审中-公开

    公开(公告)号：US20230188314A1

    公开(公告)日：2023-06-15

    申请号：US17644066

    申请日：2021-12-13

    Applicant: XILINX, INC.

    Inventor： Shaojun MA ,  Chi Fung POON ,  Kevin ZHENG ,  Parag UPADHYAYA

    IPC: H04L7/00 ,  H03K19/21

    CPC classification number: H04L7/0037 ,  H03K19/21

    Abstract: Clock generation circuitry includes quadrature locked loop circuitry having first injection locked oscillator circuitry, second injection locked oscillator circuitry, and XOR circuitry. The first injection locked oscillator circuitry receives a first input signal and a second input signal and outputs first clock signals. The first input signal and the second input signal correspond to a reference clock signal. The second injection locked oscillator circuitry is coupled to outputs of the first injection locked oscillator circuitry, and receives the first clock signals and generates second clock signals. The XOR circuitry receives the second clock signals and generates a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal. The frequencies of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are greater than the frequency of the reference clock signal.

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