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269 条记录 (耗时 0.025 秒)

    Lithographic mask alignment
    91.
    发明申请
    Lithographic mask alignment 有权
    平版印刷对准

    公开(公告)号：US20060078807A1

    公开(公告)日：2006-04-13

    申请号：US10960731

    申请日：2004-10-07

    申请人： Yong Chen

    发明人： Yong Chen

    IPC分类号： G03F9/00 ,  G03C5/00 ,  G01B11/00

    CPC分类号： G03F9/7076 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  G03F9/7042 ,  G03F9/7053

    摘要： Systems and methods of aligning a lithographic mask are described. In one aspect, a substrate and a lithographic mask are aligned based at least in part on a motive force between a substrate alignment mark on the substrate and a mask alignment mark on the lithographic mask that induces movement of at least one of the substrate and the lithographic mask into mutual alignment.

    摘要翻译： 描述了对准光刻掩模的系统和方法。 在一个方面，衬底和光刻掩模至少部分地基于衬底上的衬底对准标记和光刻掩模上的掩模对准标记之间的动力进行对准，其引起衬底和衬底中的至少一个的移动 平版印刷掩模相互对准。

    Imprinting lithography using the liquid/solid transition of metals and their alloys
    93.
    发明申请
    Imprinting lithography using the liquid/solid transition of metals and their alloys 审中-公开
    使用金属及其合金的液/固转变进行压印光刻

    公开(公告)号：US20050280147A1

    公开(公告)日：2005-12-22

    申请号：US11107136

    申请日：2005-04-14

    申请人： Yong Chen

    发明人： Yong Chen

    IPC分类号： G03F7/00 ,  H01L29/40

    CPC分类号： G03F7/0002 ,  B82Y10/00 ,  B82Y40/00

    摘要： A method is provided for imprinting a pattern having nanoscale features from a mold into the patternable layer on a substrate. The method comprises: providing the mold; forming the patternable layer on the substrate; and imprinting the mold into the patternable layer, wherein the patternable layer comprises a metal or alloy having a transition temperature from its solid form to its liquid form that is within a range of at least 10° above room temperature.

    摘要翻译： 提供了一种用于将具有纳米尺度特征的图案从模具压印到基底上的可图案层中的方法。 该方法包括：提供模具; 在所述基板上形成所述图案化层; 并将模具压印到图案化层中，其中可图案层包括具有从其固体形式到其液体形式的转变温度的金属或合金，其在高于室温的至少10°的范围内。

    Fabrication of molecular electronic circuit by imprinting
    96.
    发明授权
    Fabrication of molecular electronic circuit by imprinting 失效
    通过印记制作分子电子电路

    公开(公告)号：US06432740B1

    公开(公告)日：2002-08-13

    申请号：US09895601

    申请日：2001-06-28

    申请人： Yong Chen

    发明人： Yong Chen

    IPC分类号： H01L5140

    CPC分类号： H01L27/285 ,  B82Y10/00 ,  Y10S977/887

    摘要： A method of fabricating a molecular electronic device or crossbar memory device is provided. The device comprises at least one pair of crossed wires and a molecular switch film therebetween. The method comprises: (a) forming at least one bottom electrode on a substrate by first forming a first layer on the substrate and patterning the first layer to form the bottom electrode by an imprinting technique; (b) forming the molecular switch film on top of the bottom electrode; (c) optionally forming a protective layer on top of the molecular switch film to avoid damage thereto during further processing; (d) coating a polymer layer on top of the protective layer and patterned the polymer layer by the imprinting method to form openings that expose portions of the protective layer; and (e) forming at least one top electrode on the protective layer through the openings in the polymer layer by first forming a second layer on the polymer layer and patterning the second layer. The imprinting method can be used to fabricate nanoscale patterns over a large area at high speeds acceptable in industrial standards. Consequently, it can be used to fabricate nanoscale molecular devices, e.g., crossbar memory circuits.

    摘要翻译： 提供了一种制造分子电子器件或横向存储器件的方法。 该装置包括至少一对交叉线及其间的分子开关膜。 该方法包括：（a）在衬底上形成至少一个底部电极，首先在衬底上形成第一层，并通过刻印技术对第一层进行构图以形成底部电极; （b）在底部电极的顶部上形成分子开关膜; （c）可选地在分子开关薄膜的顶部形成保护层，以避免在进一步加工过程中损坏分子开关薄膜; （d）在保护层的顶部涂覆聚合物层，并通过压印方法对聚合物层进行图案化以形成露出保护层部分的开口; 和（e）通过首先在聚合物层上形成第二层并图案化第二层，通过聚合物层中的开口在保护层上形成至少一个顶部电极。 印刷方法可用于在工业标准中可接受的高速度大面积制造纳米尺度图案。 因此，其可以用于制造纳米级分子器件，例如交叉存储器电路。

    Integrated circuit substrate that accommodates lattice mismatch stress
    97.
    发明授权
    Integrated circuit substrate that accommodates lattice mismatch stress 有权
    集成电路基板，适应晶格失配应力

    公开(公告)号：US06429466B2

    公开(公告)日：2002-08-06

    申请号：US09774199

    申请日：2001-01-29

    申请人： Yong Chen ,  Scott W. Corzine ,  Theodore I. Kamins ,  Michael J. Ludowise ,  Pierre H. Mertz ,  Shih-Yuan Wang

    发明人： Yong Chen ,  Scott W. Corzine ,  Theodore I. Kamins ,  Michael J. Ludowise ,  Pierre H. Mertz ,  Shih-Yuan Wang

    IPC分类号： H01L31072

    CPC分类号： H01L21/7624 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02538 ,  H01L21/0254 ,  H01L21/02658 ,  H01L21/26533

    摘要： A method for growing a crystalline layer that includes a first material on a growth surface of a crystalline substrate of a second material, wherein the first material and the second material have different lattice constants. A buried layer is generated in the substrate such that the buried layer isolates a layer of the substrate that includes the growth surface from the remainder of the substrate. The second material is then deposited on the growth surface at a growth temperature. The isolated layer of the substrate has a thickness that is less than the thickness at which defects are caused in the crystalline lattice of the first material by the second material crystallizing thereon. The buried layer is sufficiently malleable at the growth temperature to allow the deformation of the lattice of the isolated layer without deforming the remainder of the substrate. The present invention may be utilized for growing III-V semiconducting material layers on silicon substrates. In the case of silicon-based substrates, the buried layer is preferably SiO2 that is sufficiently malleable at the growth temperature to allow the deformation of the isolated substrate layer.

    摘要翻译： 一种用于生长晶体层的方法，其包括在第二材料的晶体衬底的生长表面上的第一材料，其中第一材料和第二材料具有不同的晶格常数。 在衬底中产生掩埋层，使得掩埋层将衬底的包含生长表面的衬底与衬底的其余部分隔离。 然后将第二种材料在生长温度下沉积在生长表面上。 衬底的隔离层的厚度小于在其上结晶第二材料时在第一材料的晶格中产生缺陷的厚度。 掩埋层在生长温度下具有足够的延展性，以允许隔离层的晶格变形，而不使基底的其余部分变形。 本发明可用于在硅衬底上生长III-V半导体材料层。 在硅基基板的情况下，掩埋层优选是在生长温度下足够有韧性的SiO 2，以允许隔离的基底层的变形。

    Buried heterostructure for lasers and light emitting diodes
    98.
    发明授权
    Buried heterostructure for lasers and light emitting diodes 失效
    用于激光器和发光二极管的埋入异质结构

    公开(公告)号：US06327288B1

    公开(公告)日：2001-12-04

    申请号：US09263654

    申请日：1999-03-05

    申请人： Shih-Yuan Wang ,  Yong Chen

    发明人： Shih-Yuan Wang ,  Yong Chen

    IPC分类号： H01S500

    CPC分类号： B82Y20/00 ,  H01S5/2232 ,  H01S5/227 ,  H01S5/32341 ,  H01S5/34333 ,  H01S2304/00 ,  H01S2304/04 ,  H01S2304/12

    摘要： A laser diode that is constructed in a trench in a manner such that the material in the trench acts as a waveguide. The laser diode includes a first contact layer constructed from a first semiconducting material of a first carrier type, the first semiconducting material having a first index of refraction. The first contact layer has a trench therein. The trench has a layer of a second semiconducting material of the first carrier type on the bottom surface. The index of refraction of the second semiconducting material is at least one percent greater than the index of refraction of the first semiconducting material. The laser also includes a first dielectric layer covering the first layer in those regions outside of the trench and a first cladding layer constructed from a third semiconducting material of the first carrier type. The first cladding layer overlies the dielectric layer. An active layer overlies the first cladding layer. A second cladding layer constructed from a fourth semiconducting material of the opposite carrier type from the first carrier type overlies the active layer. A second contact layer of a fifth semiconducting material of the opposite carrier type from the first carrier type overlies the second cladding layer. The invention is particularly well suited for constructing laser diodes based on group III-V material systems such as GaN.

    摘要翻译： 一种激光二极管，其以沟槽中的材料作为波导的方式构造在沟槽中。 激光二极管包括由第一载体类型的第一半导体材料构成的第一接触层，第一半导体材料具有第一折射率。 第一接触层在其中具有沟槽。 沟槽在底表面上具有第一载体类型的第二半导体材料层。 第二半导体材料的折射率比第一半导体材料的折射率大至少一个百分点。 激光器还包括覆盖在沟槽外的那些区域中的第一层的第一介电层和由第一载流子类型的第三半导体材料构成的第一覆层。 第一包覆层覆盖在电介质层上。 有源层覆盖在第一覆层上。 由与第一载体类型相反的载体类型的第四半导体材料构成的第二覆层覆盖有源层。 与第一载体类型相反的载体类型的第五半导体材料的第二接触层覆盖第二覆层。 本发明特别适用于构建基于III-V族材料体系的诸如GaN的激光二极管。

    Reduction of threading dislocations by amorphization and recrystallization
    100.
    发明授权
    Reduction of threading dislocations by amorphization and recrystallization 失效
    通过非晶化和重结晶减少穿透位错

    公开(公告)号：US5927995A

    公开(公告)日：1999-07-27

    申请号：US833813

    申请日：1997-04-09

    申请人： Yong Chen ,  Richard P. Schneider, Jr. ,  Shih-Yun Wang

    发明人： Yong Chen ,  Richard P. Schneider, Jr. ,  Shih-Yun Wang

    IPC分类号： H01L21/20 ,  H01L21/265

    CPC分类号： H01L21/0254 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02664 ,  H01L21/02667

    摘要： A method for providing an epitaxial layer of a first material over a substrate comprising a second material having a lattice constant different from that of the first material. In the method of the present invention, a first layer of the first material is grown on the substrate. A portion of the first layer is treated to render that portion amorphous. The amorphous portion is then annealed at a temperature above the recrystallization point of the amorphous portion, but below the melting point of the crystallized portion of the first layer thereby recrystallizing the amorphous portion of the first layer. The first layer may rendered amorphous by ion implantation. The method may be used to generate GaN layers on sapphire having fewer dislocations than GaN layers generated by conventional deposition techniques.

    摘要翻译： 一种用于在衬底上提供第一材料的外延层的方法，包括具有不同于第一材料的晶格常数的第二材料。 在本发明的方法中，第一材料的第一层在衬底上生长。 处理第一层的一部分以使该部分成为无定形的。 然后将非晶部分在高于非晶部分的再结晶点的温度下退火，但低于第一层的结晶部分的熔点，从而使第一层的非晶部分重结晶。 第一层可以通过离子注入形成非晶态。 该方法可用于在具有比通过常规沉积技术产生的GaN层更少的位错的蓝宝石上生成GaN层。