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    Semiconductor integrated circuit device and a method of fabricating the same
    91.
    发明申请
    Semiconductor integrated circuit device and a method of fabricating the same 有权
    半导体集成电路器件及其制造方法

    公开(公告)号：US20080217616A1

    公开(公告)日：2008-09-11

    申请号：US12073315

    申请日：2008-03-04

    申请人： Yong-hoon Son ,  Si-young Choi ,  Jong-wook Lee

    发明人： Yong-hoon Son ,  Si-young Choi ,  Jong-wook Lee

    IPC分类号： H01L29/04 ,  H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/66795

    摘要： A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.

    摘要翻译： 一种制造半导体集成电路的方法包括在半导体衬底上形成第一电介质层，图案化第一电介质层以形成第一图案化电介质层，在第一图案化电介质层上形成非单晶种子层， 的种子层以形成图案化种子层，在第一图案化介电层和图案化种子层上形成第二介电层，去除第二介电层的部分以形成第二图案化电介质层，将图案化种子层照射到单个 将图案化种子层结晶，去除第一图案化电介质层和第二图案化电介质层的部分，使得单结晶种子层相对于第一和/或第二图案化电介质层在垂直方向上突出，并且形成 与单晶活性图案接触的栅电极。

    Methods of Forming Single Crystalline Layers and Methods of Manufacturing Semiconductor Devices Having Such Layers
    92.
    发明申请
    Methods of Forming Single Crystalline Layers and Methods of Manufacturing Semiconductor Devices Having Such Layers 有权
    形成单晶层的方法和制造具有这种层的半导体器件的方法

    公开(公告)号：US20070218607A1

    公开(公告)日：2007-09-20

    申请号：US11751857

    申请日：2007-05-22

    申请人： Yong-Hoon Son ,  Si-Young Choi ,  Jong-Wook Lee

    发明人： Yong-Hoon Son ,  Si-Young Choi ,  Jong-Wook Lee

    IPC分类号： H01L21/84

    CPC分类号： H01L21/02675 ,  H01L21/02532 ,  H01L21/02645 ,  H01L21/2026 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688

    摘要： In a method of forming a single crystalline semiconductor layer, an amorphous layer may be formed on a seed layer that includes a single crystalline material. The single crystalline layer may be formed from the amorphous layer by irradiating a laser beam onto the amorphous layer using the seed layer as a seed for a phase change of the amorphous layer. The laser beam may have an energy for melting the amorphous layer, and the laser beam may be irradiated onto the amorphous layer without generating a superimposedly irradiated region of the amorphous layer. The single crystalline layer may include a high density of large-sized grains without generating a protrusion thereon through a simple process so that a semiconductor device including the single crystalline layer may have a high degree of integration and improved electrical characteristics.

    摘要翻译： 在形成单晶半导体层的方法中，可以在包括单晶材料的籽晶层上形成非晶层。 可以通过使用种子层作为非晶层相变的种子将激光束照射到非晶层上，由非晶层形成单晶层。 激光束可以具有用于熔化非晶层的能量，并且可以将激光束照射到非晶层上而不产生非晶层的叠加照射的区域。 单晶层可以包括高密度的大尺寸晶粒，而不通过简单的工艺在其上产生突起，使得包括单晶层的半导体器件可以具有高度集成度和改善的电特性。

    Multi-structured Si-fin
    93.
    发明授权
    Multi-structured Si-fin 失效
    多结构Si-fin

    公开(公告)号：US07141856B2

    公开(公告)日：2006-11-28

    申请号：US10778147

    申请日：2004-02-17

    申请人： Deok Hyung Lee ,  Byeong Chan Lee ,  In Soo Jung ,  Yong Hoon Son ,  Siyoung Choi ,  Taek Jung Kim

    发明人： Deok Hyung Lee ,  Byeong Chan Lee ,  In Soo Jung ,  Yong Hoon Son ,  Siyoung Choi ,  Taek Jung Kim

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L21/823412 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823437 ,  H01L29/66795 ,  H01L29/7851

    摘要： Disclosed is a semiconductor fin construction useful in FinFET devices that incorporates an upper region and a lower region with wherein the upper region is formed with substantially vertical sidewalls and the lower region is formed with inclined sidewalls to produce a wider base portion. The disclosed semiconductor fin construction will also typically include a horizontal step region at the interface between the upper region and the lower region. Also disclosed are a series of methods of manufacturing semiconductor devices incorporating semiconductor fins having this dual construction and incorporating various combinations of insulating materials such as silicon dioxide and/or silicon nitride for forming shallow trench isolation (STI) structures between adjacent semiconductor fins.

    摘要翻译： 公开了一种可用于FinFET器件的半导体鳍片结构，其结合了上部区域和下部区域，其中上部区域形成有基本上垂直的侧壁，并且下部区域形成有倾斜的侧壁以产生更宽的基部。 所公开的半导体鳍片结构通常还将包括在上部区域和下部区域之间的界面处的水平台阶区域。 还公开了一系列制造具有这种双重结构的半导体鳍片的半导体器件的方法，并结合了诸如二氧化硅和/或氮化硅的绝缘材料的各种组合，用于在相邻的半导体鳍片之间形成浅沟槽隔离（STI）结构。

    Heterogeneous group IV semiconductor substrates, integrated circuits formed on such substrates, and related methods
    96.
    发明申请
    Heterogeneous group IV semiconductor substrates, integrated circuits formed on such substrates, and related methods 有权
    异质IV族半导体衬底，形成在这种衬底上的集成电路及相关方法

    公开(公告)号：US20050218395A1

    公开(公告)日：2005-10-06

    申请号：US11080737

    申请日：2005-03-15

    申请人： Sung-Min Kim ,  Kyoung-Hwan Yeo ,  In-Soo Jung ,  Si-Young Choi ,  Dong-Won Kim ,  Yong-Hoon Son ,  Young-Eun Lee ,  Byeong-Chan Lee ,  Jong-Wook Lee

    发明人： Sung-Min Kim ,  Kyoung-Hwan Yeo ,  In-Soo Jung ,  Si-Young Choi ,  Dong-Won Kim ,  Yong-Hoon Son ,  Young-Eun Lee ,  Byeong-Chan Lee ,  Jong-Wook Lee

    IPC分类号： H01L21/20 ,  H01L29/06 ,  H01L29/78

    CPC分类号： H01L29/0653 ,  H01L29/78

    摘要： Embodiments of the present invention include heterogeneous substrates, integrated circuits formed on such heterogeneous substrates, and methods of forming such substrates and integrated circuits. The heterogeneous substrates according to certain embodiments of the present invention include a first Group IV semiconductor layer (e.g., silicon), a second Group IV pattern (e.g., a silicon-germanium pattern) that includes a plurality of individual elements on the first Group IV semiconductor layer, and a third Group IV semiconductor layer (e.g., a silicon epitaxial layer) on the second Group IV pattern and on a plurality of exposed portions of the first Group IV semiconductor layer. The second Group IV pattern may be removed in embodiments of the present invention. In these and other embodiments of the present invention, the third Group IV semiconductor layer may be planarized.

    摘要翻译： 本发明的实施例包括异质衬底，在这种异质衬底上形成的集成电路，以及形成这种衬底和集成电路的方法。 根据本发明的某些实施方案的异质衬底包括第一组IV半导体层（例如，硅），第二组IV图案（例如硅 - 锗图案），其包括第一组IV上的多个单独元件 半导体层和第二组IV模式上的第三组IV半导体层（例如，硅外延层）和第一组IV半导体层的多个暴露部分上。 在本发明的实施例中可以去除第二组IV图案。 在本发明的这些和其它实施例中，第三组IV半导体层可以被平坦化。

    Methods for fabricating fin field effect transistors using a protective layer to reduce etching damage
    98.
    发明申请
    Methods for fabricating fin field effect transistors using a protective layer to reduce etching damage 失效
    使用保护层制造鳍状场效应晶体管以减少蚀刻损伤的方法

    公开(公告)号：US20050019993A1

    公开(公告)日：2005-01-27

    申请号：US10869764

    申请日：2004-06-16

    申请人： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son ,  In-Soo Jung

    发明人： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son ,  In-Soo Jung

    IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L21/00 ,  H01L21/44 ,  H01L21/8242

    CPC分类号： H01L29/7851 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66795

    摘要： A method of forming a fin field effect transistor on a semiconductor substrate includes forming a vertical fin protruding from the substrate. A buffer oxide liner is formed on a top surface and on sidewalls of the fin. A trench is then formed on the substrate, where at least a portion of the fin protrudes from a bottom surface of the trench. The trench may be formed by forming a dummy gate on at least a portion of the fin, forming an insulation layer on the fin surrounding the dummy gate, and then removing the dummy gate to expose the at least a portion of the fin, such that the trench is surrounded by the insulation layer. The buffer oxide liner is then removed from the protruding portion of the fin, and a gate is formed in the trench on the protruding portion of the fin.

    摘要翻译： 在半导体衬底上形成鳍状场效应晶体管的方法包括形成从衬底突出的垂直翅片。 缓冲氧化物衬垫形成在翅片的顶表面和侧壁上。 然后在衬底上形成沟槽，其中鳍的至少一部分从沟槽的底表面突出。 可以通过在鳍片的至少一部分上形成伪栅极来形成沟槽，在围绕虚拟栅极的鳍片上形成绝缘层，然后去除伪栅极以暴露鳍片的至少一部分，使得 沟槽被绝缘层包围。 然后从鳍片的突出部分去除缓冲氧化物衬垫，并且在鳍片的突出部分上的沟槽中形成栅极。

    SEMICONDUCTOR DEVICE INCLUDING CHANNEL STRUCTURE
    99.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING CHANNEL STRUCTURE 有权

    公开(公告)号：US20180130816A1

    公开(公告)日：2018-05-10

    申请号：US15585211

    申请日：2017-05-03

    申请人： Yong Hoon SON ,  Yoon Jae KIM ,  Seok Woo NAM

    发明人： Yong Hoon SON ,  Yoon Jae KIM ,  Seok Woo NAM

    IPC分类号： H01L27/11582

    CPC分类号： H01L27/11582 ,  H01L27/11565

    摘要： A semiconductor device includes a stacked structure disposed on a semiconductor substrate. The stacked structure includes interlayer insulating layers and gate electrodes, alternately stacked. Separation patterns are disposed to penetrate the stacked structure. A channel structure is disposed between the separation patterns. The channel structure includes a horizontal portion interposed between the stacked structure and the semiconductor substrate while being in contact with the semiconductor substrate and includes vertical portions extending from the horizontal portion in a vertical direction and penetrating the stacked structure. A lower structure is interposed between the horizontal portion and the separation patterns. A dielectric structure is interposed between the vertical portions and the stacked structure and extends between the horizontal portion and the stacked structure.