公开(公告)号：US20060211260A1

公开(公告)日：2006-09-21

申请号：US11214544

申请日：2005-08-29

申请人： Luan Tran ,  William Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi (Jenny) Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer Abatchev ,  Gurtej Sandhu ,  D. Durcan

发明人： Luan Tran ,  William Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi (Jenny) Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer Abatchev ,  Gurtej Sandhu ,  D. Durcan

IPC分类号： H01L21/31

CPC分类号： H01L21/0338 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3088

摘要： Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC. The combined pattern made out by the first pattern and the second pattern is transferred to an underlying amorphous silicon layer and the pattern is subjected to a carbon strip to remove BARC and photoresist material. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, having features of difference sizes, is then etched into the underlying substrate through the amorphous carbon hard mask layer.

摘要翻译： 通过使用通过组合两个单独形成的图案形成的掩模蚀刻衬底来形成集成电路的不同尺寸的特征。 间距乘法用于形成第一图案的相对较小的特征以及用于形成第二图案的较大特征的常规光刻。 间距倍增通过对光致抗蚀剂进行图案化，然后将该图案蚀刻成无定形碳层来实现。 然后在无定形碳的侧壁上形成侧壁间隔物。 去除无定形碳，留下限定第一掩模图案的侧壁间隔物。 然后将底部抗反射涂层（BARC）沉积在间隔物周围以形成平坦表面，并且在BARC上形成光致抗蚀剂层。 接下来通过常规光刻法将光致抗蚀剂图案化以形成第二图案，然后将其转印到BARC。 通过第一图案和第二图案形成的组合图案被转印到下面的非晶硅层，并且图案经受碳带以去除BARC和光致抗蚀剂材料。 然后将组合图案转移到氧化硅层，然后转移到无定形碳掩模层。 具有不同尺寸特征的组合掩模图案然后通过无定形碳硬掩模层蚀刻到下面的衬底中。

公开(公告)号：US20060211201A1

公开(公告)日：2006-09-21

申请号：US11440351

申请日：2006-05-24

申请人： Sukesh Sandhu ,  Gurtej Sandhu

发明人： Sukesh Sandhu ,  Gurtej Sandhu

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7881

摘要： A first dielectric layer is formed over a substrate. A single layer first conductive layer that acts as a floating gate is formed over the first dielectric layer. A trough is formed in the first conductive layer to increase the capacitive coupling of the floating gate with a control gate. An intergate dielectric layer is formed over the floating gate layer. A second conductive layer is formed over the second dielectric layer to act as a control gate.

公开(公告)号：US20060172088A1

公开(公告)日：2006-08-03

申请号：US11394989

申请日：2006-03-30

申请人： Cem Basceri ,  Irina Vasilyeva ,  Ammar Derraa ,  Philip Campbell ,  Gurtej Sandhu

发明人： Cem Basceri ,  Irina Vasilyeva ,  Ammar Derraa ,  Philip Campbell ,  Gurtej Sandhu

IPC分类号： C23C16/14

CPC分类号： H01L21/28518 ,  C23C16/42 ,  H01L21/28556

摘要： Chemical vapor deposition methods of forming titanium silicide including layers on substrates are disclosed. TiCl4 and at least one silane are first fed to the chamber at or above a first volumetric ratio of TiCl4 to silane for a first period of time. The ratio is sufficiently high to avoid measurable deposition of titanium silicide on the substrate. Alternately, no measurable silane is fed to the chamber for a first period of time. Regardless, after the first period, TiCl4 and at least one silane are fed to the chamber at or below a second volumetric ratio of TiCl4 to silane for a second period of time. If at least one silane was fed during the first period of time, the second volumetric ratio is lower than the first volumetric ratio. Regardless, the second feeding is effective to plasma enhance chemical vapor deposit a titanium silicide including layer on the substrate.

公开(公告)号：US20060089002A1

公开(公告)日：2006-04-27

申请号：US11292449

申请日：2005-12-02

申请人： Gurtej Sandhu

发明人： Gurtej Sandhu

IPC分类号： H01L21/311

CPC分类号： H01L21/02271 ,  H01L21/02126 ,  H01L21/02129 ,  H01L21/02131 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02321 ,  H01L21/3105 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3115 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/31695 ,  H01L21/76819 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10858 ,  H01L27/10873

摘要： In a DRAM fabrication process, a first oxide is provided over a transistor gate and over a substrate extending from under the gate. The deposition is non-conformal in that the oxide is thicker over the gate and over the substrate than it is on the side of the gate. A second non-conformal oxide is provided over the first non-conformal oxide. The second oxide is annealed in a boron-containing atmosphere, and the first oxide prevents boron diffusion from the second oxide into the gate and substrate. The second oxide may then serve as an etch stop, a CMP stop, or both.

公开(公告)号：US20060081911A1

公开(公告)日：2006-04-20

申请号：US11296385

申请日：2005-12-08

申请人： Shubneesh Batra ,  Gurtej Sandhu

发明人： Shubneesh Batra ,  Gurtej Sandhu

IPC分类号： H01L29/788

CPC分类号： H01L21/28185 ,  B82Y10/00 ,  G11C16/0416 ,  G11C2216/06 ,  H01L21/28194 ,  H01L29/40114 ,  H01L29/42332 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66825 ,  H01L29/7883 ,  Y10S977/943

摘要： The invention provides a method of forming an electron memory storage device and the resulting device. The device comprises a gate structure which, in form, comprises a first gate insulating layer formed over a semiconductor substrate, a self-forming electron trapping layer of noble metal nano-crystals formed over the first gate insulating layer, a second gate insulating layer formed over the electron trapping layer, a gate electrode formed over the second gate insulating layer, and source and drain regions formed on opposite sides of the gate structure.

公开(公告)号：US20060065368A1

公开(公告)日：2006-03-30

申请号：US11281657

申请日：2005-11-17

申请人： Gurtej Sandhu

发明人： Gurtej Sandhu

IPC分类号： H01L21/306 ,  C23F1/00

CPC分类号： C23C16/4558 ,  C23C16/045 ,  C23C16/45563 ,  C23C16/45589 ,  C23C16/52

摘要： A gas delivery device useful in material deposition processes executed during semiconductor device fabrication in a reaction chamber, including the gas delivery device of the present invention and a method for carrying out a material deposition process, including introducing process gas into a reaction chamber using the gas delivery device of the present invention. In each embodiment, the gas delivery device of the present invention includes a plurality of active diffusers and a plurality of gas delivery nozzles, which extend into the reaction chamber. Before entering the reaction chamber through one of the plurality of gas delivery nozzles, process gas must first pass through one of the plurality active diffusers. Each of the active diffusers is centrally controllable such that the rate at which process gas flows through each active diffuser is exactly controlled at all times throughout a given deposition process.

摘要翻译： 一种气体输送装置，其用于在包括本发明的气体输送装置的反应室中的半导体器件制造期间执行的材料沉积工艺中的材料沉积工艺以及用于执行材料沉积工艺的方法，包括使用气体将工艺气体引入反应室 输送装置。 在每个实施例中，本发明的气体输送装置包括多个活性扩散器和延伸到反应室中的多个气体输送喷嘴。 在通过多个气体输送喷嘴之一进入反应室之前，处理气体必须首先通过多个活性扩散器中的一个。 每个活性扩散器都是可中央控制的，使得在给定的沉积过程中，工艺气体流过每个有源扩散器的速率在任何时候被精确地控制。

公开(公告)号：US20060046440A1

公开(公告)日：2006-03-02

申请号：US10932151

申请日：2004-09-01

申请人： Nirmal Ramaswamy ,  Gurtej Sandhu ,  Chris Carlson ,  F. Gealy

发明人： Nirmal Ramaswamy ,  Gurtej Sandhu ,  Chris Carlson ,  F. Gealy

IPC分类号： H01L21/20

CPC分类号： H01L29/66787 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02491 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/02658

摘要： The invention includes methods of forming layers comprising epitaxial silicon. In one implementation, an opening is formed within a first material received over a monocrystalline material. Opposing sidewalls of the opening are lined with a second material, with monocrystalline material being exposed at a base of the second material-lined opening. A silicon-comprising layer is epitaxially grown from the exposed monocrystalline material within the second material-lined opening. At least a portion of the second material lining is in situ removed. Other aspects and implementations are contemplated.

公开(公告)号：US20060046419A1

公开(公告)日：2006-03-02

申请号：US11021639

申请日：2004-12-22

申请人： Gurtej Sandhu ,  Kevin Shea ,  Chris Hill ,  Kevin Torek

发明人： Gurtej Sandhu ,  Kevin Shea ,  Chris Hill ,  Kevin Torek

IPC分类号： H01L21/20

CPC分类号： H01L28/91 ,  H01L27/10852

摘要： Double-sided container capacitors are formed using sacrificial layers. A sacrificial layer is formed within a recess in a structural layer. A lower electrode is formed within the recess. The sacrificial layer is removed to create a space to allow access to the sides of the structural layer. The structural layer is removed, creating an isolated lower electrode. The lower electrode can be covered with a capacitor dielectric and upper electrode to form a double-sided container capacitor.

摘要翻译： 使用牺牲层形成双面容器电容器。 在结构层的凹部内形成牺牲层。 下部电极形成在凹部内。 去除牺牲层以产生允许接近结构层的侧面的空间。 去除结构层，形成隔离的下电极。 下电极可以用电容器电介质和上电极覆盖以形成双面容器电容器。

公开(公告)号：US20060046200A1

公开(公告)日：2006-03-02

申请号：US10932993

申请日：2004-09-01

申请人： Mirzafer Abatchev ,  Gurtej Sandhu

发明人： Mirzafer Abatchev ,  Gurtej Sandhu

IPC分类号： G03F7/00

CPC分类号： H01L21/308 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32139

摘要： The dimensions of mask patterns, such as pitch-multiplied spacers, are controlled by controlled growth of features in the patterns after they are formed. To form a pattern of pitch-multiplied spacers, a pattern of mandrels is first formed overlying a semiconductor substrate. Spacers are then formed on sidewalls of the mandrels by depositing a blanket layer of material over the mandrels and preferentially removing spacer material from horizontal surfaces. The mandrels are then selectively removed, leaving behind a pattern of freestanding spacers. The spacers comprise a material, such as polysilicon and amorphous silicon, known to increase in size upon being oxidized. The spacers are oxidized to grow them to a desired width. After reaching the desired width, the spacers can be used as a mask to pattern underlying layers and the substrate. Advantageously, because the spacers are grown by oxidation, thinner blanket layers can be deposited over the mandrels, thereby allowing the deposition of more conformal blanket layers and widening the process window for spacer formation.

公开(公告)号：US20060040056A1

公开(公告)日：2006-02-23

申请号：US11257946

申请日：2005-10-24

申请人： Gurtej Sandhu

发明人： Gurtej Sandhu

IPC分类号： C23C16/00

CPC分类号： H01L21/02181 ,  C23C16/0236 ,  C23C16/45531 ,  H01L21/02178 ,  H01L21/02205 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/3141 ,  H01L21/31645 ,  H01L29/517

摘要： The invention includes methods of forming material on a substrate and methods of forming a field effect transistor gate oxide. In one implementation, a first species monolayer is chemisorbed onto a substrate within a chamber from a gaseous first precursor. The first species monolayer is discontinuously formed over the substrate. The substrate having the discontinuous first species monolayer is exposed to a gaseous second precursor different from the first precursor effective to react with the first species to form a second species monolayer, and effective to form a reaction product of the second precursor with substrate material not covered by the first species monolayer. The substrate having the second species monolayer and the reaction product is exposed to a third gaseous substance different from the first and second precursors effective to selectively remove the reaction product from the substrate relative to the second species monolayer. Other implementations are contemplated.