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91.发明申请Method for production of deep p regions in silicon, and semiconductor components produced using the method 有权用于生产硅中的深p区的方法以及使用该方法制造的半导体元件公开(公告)号：US20050164476A1
公开(公告)日：2005-07-28
申请号：US11023039
申请日：2004-12-23
IPC分类号： H01L21/329 , H01L21/331 , H01L21/332 , H01L21/336 , H01L27/08 , H01L29/06 , H01L29/32 , H01L21/425 , H01L21/8222
CPC分类号： H01L29/66712 , H01L21/263 , H01L27/0814 , H01L27/0817 , H01L29/0634 , H01L29/32 , H01L29/66136 , H01L29/66333 , H01L29/66363
摘要： The invention relates to a method for production of deep p regions in silicon, with the method having the following step: bombardment of an n substrate section, an n epitaxial section or an exposed weakly doped n region of a semiconductor component that is to be produced with high-energy particles, whose energy is chosen such that the previous n region is redoped to form a p region to the desired depth after a specific healing time at a specific healing temperature after the bombardment, and to its use for the production of semiconductor components, for example in order to carry out isolating diffusion.
摘要翻译： 本发明涉及一种用于生产硅中深p区的方法，该方法具有以下步骤：轰击要制备的半导体组分的n衬底部分，n外延部分或暴露的弱掺杂n区域 具有高能粒子，其能量被选择为使得先前的n区域被重新加工以在轰击之后的特定愈合温度下的特定愈合时间之后形成到所需深度的ap区域，并且用于生产半导体部件 ，例如为了进行隔离扩散。
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公开(公告)号：US06727526B1
公开(公告)日：2004-04-27
申请号：US10089590
申请日：2002-04-05
IPC分类号： H01L2974
CPC分类号： H01L29/7432 , H01L29/0834 , H01L29/7404
摘要： A preferably asymetrical thyristor (1) with at least one driver stage (20) for amplifying a control current (I) fed into the cathodal base (16) of the thyristor, in which, in the driver stage, the transistor gain factors &agr;npn and &agr;pnp are in each case greater than, preferably, in the thyristor and anode short circuits of the thyristor (174) have a smaller electrical conductivity in the driver stage than in the thyristor.
摘要翻译： 优选的不对称晶闸管（1）具有至少一个驱动级（20），用于放大馈送到晶闸管的阴极基极（16）中的控制电流（I），其中在驱动级中，晶体管增益因子alphanpn和 在每种情况下，在可控硅中大大优选地，可控硅和阳极短路在驱动级具有比在晶闸管中更小的导电性。
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93.发明授权Soft switching semiconductor component with high robustness and low switching losses 有权软开关半导体元件具有高鲁棒性和低开关损耗公开(公告)号：US07812427B2
公开(公告)日：2010-10-12
申请号：US11757451
申请日：2007-06-04
IPC分类号： H01L29/06
CPC分类号： H01L29/861 , H01L21/263 , H01L29/063 , H01L29/7395 , H01L29/74
摘要： A semiconductor component includes a semiconductor body and a second semiconductor zone of a first conductivity type that serves as a rear side emitter. The second semiconductor zone is preceded by a plurality of third semiconductor zones of a second conductivity type that is opposite to the first conductivity type. The third semiconductor zones are spaced apart from one another in a lateral direction. In addition, provided within the semiconductor body is a field stop zone spaced apart from the second semiconductor zone, thereby reducing an electric field in the direction toward the second semiconductor zone.
摘要翻译： 半导体部件包括半导体主体和用作后侧发射极的第一导电类型的第二半导体区。 第二半导体区域之前是与第一导电类型相反的多个第二导电类型的第三半导体区域。 第三半导体区域在横向彼此间隔开。 此外，设置在半导体本体内的是与第二半导体区间隔开的场阻挡区域，从而减小朝向第二半导体区域的方向的电场。
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94.发明授权Diode having one or more zones of a first conductivity type and one or more zones of a second conductivity type each located within a layer of the second conductivity type 有权二极管具有一个或多个第一导电类型的区域和一个或多个第二导电类型的区域，每个区域都位于第二导电类型的层内公开(公告)号：US07687891B2
公开(公告)日：2010-03-30
申请号：US11748050
申请日：2007-05-14
IPC分类号： H01L29/06 , H01L29/861
CPC分类号： H01L29/7395 , H01L27/0761 , H01L29/0623 , H01L29/0834 , H01L29/8613 , H01L29/87
摘要： A semiconductor device includes a first layer having a first conductivity type, a second layer having a second conductivity type, a third layer having the second conductivity type, one or more first zones having the first conductivity type and located within the second layer, wherein each one of the one or more first zones is adjacent to the third layer, and one or more second zones having the second conductivity type and located within the second layer, wherein each one of the one or more second zones is adjacent to one or more of the one or more first zones.
摘要翻译： 半导体器件包括具有第一导电类型的第一层，具有第二导电类型的第二层，具有第二导电类型的第三层，具有第一导电类型并位于第二层内的一个或多个第一区， 所述一个或多个第一区域中的一个与所述第三层相邻，以及具有所述第二导电类型并且位于所述第二层内的一个或多个第二区域，其中所述一个或多个第二区域中的每一个与所述第二区域中的一个或多个相邻 一个或多个第一区域。
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公开(公告)号：US20080283868A1
公开(公告)日：2008-11-20
申请号：US11748050
申请日：2007-05-14
IPC分类号： H01L29/739 , H01L21/329 , H01L29/861 , H01L21/331
CPC分类号： H01L29/7395 , H01L27/0761 , H01L29/0623 , H01L29/0834 , H01L29/8613 , H01L29/87
摘要： A semiconductor device includes a first layer having a first conductivity type, a second layer having a second conductivity type, a third layer having the second conductivity type, one or more first zones having the first conductivity type and located within the second layer, wherein each one of the one or more first zones is adjacent to the third layer, and one or more second zones having the second conductivity type and located within the second layer, wherein each one of the one or more second zones is adjacent to one or more of the one or more first zones.
摘要翻译： 半导体器件包括具有第一导电类型的第一层，具有第二导电类型的第二层，具有第二导电类型的第三层，具有第一导电类型并位于第二层内的一个或多个第一区， 所述一个或多个第一区域中的一个与所述第三层相邻，以及具有所述第二导电类型并且位于所述第二层内的一个或多个第二区域，其中所述一个或多个第二区域中的每一个与所述第二区域中的一个或多个相邻 一个或多个第一区域。
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96.发明申请Soft Switching Semiconductor Component with High Robustness and Low Switching Losses 有权具有高稳定性和低开关损耗的软开关半导体元件公开(公告)号：US20070278472A1
公开(公告)日：2007-12-06
申请号：US11757451
申请日：2007-06-04
IPC分类号： H01L29/06
CPC分类号： H01L29/861 , H01L21/263 , H01L29/063 , H01L29/7395 , H01L29/74
摘要： A semiconductor component includes a semiconductor body and a second semiconductor zone of a first conductivity type that serves as a rear side emitter. The second semiconductor zone is preceded by a plurality of third semiconductor zones of a second conductivity type that is opposite to the first conductivity type. The third semiconductor zones are spaced apart from one another in a lateral direction. In addition, provided within the semiconductor body is a field stop zone spaced apart from the second semiconductor zone, thereby reducing an electric field in the direction toward the second semiconductor zone.
摘要翻译： 半导体部件包括半导体主体和用作后侧发射极的第一导电类型的第二半导体区。 第二半导体区域之前是与第一导电类型相反的多个第二导电类型的第三半导体区域。 第三半导体区域在横向彼此间隔开。 此外，设置在半导体本体内的是与第二半导体区间隔开的场阻挡区域，从而减小朝向第二半导体区域的方向的电场。
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97.发明授权IGBT having one or more stacked zones formed within a second layer of the IGBT 有权IGBT具有形成在IGBT的第二层内的一个或多个堆叠区公开(公告)号：US07915675B2
公开(公告)日：2011-03-29
申请号：US12702627
申请日：2010-02-09
CPC分类号： H01L29/7395 , H01L27/0761 , H01L29/0623 , H01L29/0834 , H01L29/8613 , H01L29/87
摘要： An IGBT includes a first region, a second region located within the first region, a first contact coupled to the first region, a first layer arranged below the first region, a gate overlying at least a portion of the first region between the second region and the first layer and a second layer formed under the first layer. One or more stacked zones are formed within the second layer. Each one or more stacked zones includes a first zone and a second zone that overlies the first zone. Each first zone is inversely doped with respect to the second layer and each second zone is inversely doped with respect to the first zone. The IGBT further includes a third layer formed under the second layer and a second contact coupled to the third layer.
摘要翻译： IGBT包括第一区域，位于第一区域内的第二区域，耦合到第一区域的第一触点，布置在第一区域下方的第一层，覆盖第二区域和第二区域的至少一部分的栅极， 第一层和形成在第一层下面的第二层。 在第二层内形成一个或多个堆叠区。 每个一个或多个堆叠区域包括覆盖在第一区域上的第一区域和第二区域。 每个第一区域相对于第二层是反掺杂的，并且每个第二区域相对于第一区域是反掺杂的。 IGBT还包括形成在第二层下面的第三层和耦合到第三层的第二接触。
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98.发明申请IGBT Having One or More Stacked Zones Formed within a Second Layer of the IGBT 有权IGBT在IGBT的第二层内形成一个或多个堆叠区公开(公告)号：US20100148215A1
公开(公告)日：2010-06-17
申请号：US12702627
申请日：2010-02-09
IPC分类号： H01L29/739 , H01L21/331
CPC分类号： H01L29/7395 , H01L27/0761 , H01L29/0623 , H01L29/0834 , H01L29/8613 , H01L29/87
摘要： An IGBT includes a first region, a second region located within the first region, a first contact coupled to the first region, a first layer arranged below the first region, a gate overlying at least a portion of the first region between the second region and the first layer and a second layer formed under the first layer. One or more stacked zones are formed within the second layer. Each one or more stacked zones includes a first zone and a second zone that overlies the first zone. Each first zone is inversely doped with respect to the second layer and each second zone is inversely doped with respect to the first zone. The IGBT further includes a third layer formed under the second layer and a second contact coupled to the third layer.
摘要翻译： IGBT包括第一区域，位于第一区域内的第二区域，耦合到第一区域的第一触点，布置在第一区域下方的第一层，覆盖第二区域和第二区域的至少一部分的栅极， 第一层和形成在第一层下面的第二层。 在第二层内形成一个或多个堆叠区。 每个一个或多个堆叠区域包括覆盖在第一区域上的第一区域和第二区域。 每个第一区域相对于第二层是反掺杂的，并且每个第二区域相对于第一区域是反掺杂的。 IGBT还包括形成在第二层下面的第三层和耦合到第三层的第二接触。
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公开(公告)号：US09245760B2
公开(公告)日：2016-01-26
申请号：US12895664
申请日：2010-09-30
申请人： Anton Mauder , Hans-Joachim Schulze , Hans-Joerg Timme , Franz Hirler , Francisco Javier Santos Rodriguez
发明人： Anton Mauder , Hans-Joachim Schulze , Hans-Joerg Timme , Franz Hirler , Francisco Javier Santos Rodriguez
IPC分类号： H01L21/20 , H01L21/306 , H01L21/02 , H01L21/78 , H01L29/78
CPC分类号： H01L29/2003 , H01L21/0237 , H01L21/02381 , H01L21/0245 , H01L21/02513 , H01L21/02521 , H01L21/02532 , H01L21/0254 , H01L21/0262 , H01L21/306 , H01L21/30621 , H01L21/3065 , H01L21/324 , H01L21/78 , H01L29/045 , H01L29/45 , H01L29/7846 , H01L29/7848
摘要： In one embodiment, a method of forming a semiconductor device includes forming a first porous semiconductor layer over a top surface of a substrate. A first epitaxial layer is formed over the first porous semiconductor layer. A circuitry is formed within and over the first epitaxial layer. The circuitry is formed without completely oxidizing the first epitaxial layer.
摘要翻译： 在一个实施例中，形成半导体器件的方法包括在衬底的顶表面上形成第一多孔半导体层。 在第一多孔半导体层上形成第一外延层。 在第一外延层内和上方形成电路。 在不完全氧化第一外延层的情况下形成电路。
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100.发明申请公开(公告)号：US20140001552A1
公开(公告)日：2014-01-02
申请号：US13539973
申请日：2012-07-02
申请人： Franz Hirler , Hans Weber , Hans-Joachim Schulze , Uwe Wahl
发明人： Franz Hirler , Hans Weber , Hans-Joachim Schulze , Uwe Wahl
IPC分类号： H01L29/772 , H01L21/20 , H01L29/02
CPC分类号： H01L29/66712 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/0696 , H01L29/1095 , H01L29/161 , H01L29/167 , H01L29/408 , H01L29/7395 , H01L29/7811 , H01L29/8611
摘要： A drift layer of a super junction semiconductor device includes first portions of a first conductivity type and second portions of a second conductivity type opposite to the first conductivity type. The first and second portions are formed both in a cell area and in an edge area surrounding the cell area, wherein an on-state or forward current through the drift layer flows through the first portions in the cell area. At least one of the first and second portions other than the first portions in the cell area includes an auxiliary structure or contains auxiliary impurities to locally reduce the avalanche rate. Locally reducing the avalanche rate increases the total voltage blocking capability of the super junction semiconductor device.
摘要翻译： 超结半导体器件的漂移层包括第一导电类型的第一部分和与第一导电类型相反的第二导电类型的第二部分。 第一和第二部分在单元区域和围绕单元区域的边缘区域中形成，其中通过漂移层的导通状态或正向电流流过单元区域中的第一部分。 电池区域中除了第一部分之外的第一和第二部分中的至少一个包括辅助结构或包含辅助杂质以局部降低雪崩率。 本地降低雪崩率提高了超结半导体器件的总电压阻断能力。
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