公开(公告)号：US10199464B2

公开(公告)日：2019-02-05

申请号：US15438114

申请日：2017-02-21

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Cheng Chi ,  Chi-Chun Liu ,  Ruilong Xie ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/66

Abstract: Techniques for VFET top source and drain epitaxy are provided. In one aspect, a method of forming a VFET includes: patterning a fin to form a bottom source/drain region and a fin channel of the VFET; forming bottom spacers on the bottom source/drain region; depositing a high-κ gate dielectric onto the bottom spacers and along sidewalls of the fin channel; forming gates over the bottom spacers; forming top spacers on the gates; partially recessing the fin channel to create a trench between the top spacers; forming a nitride liner along sidewalls of the trench; fully recessing the fin channel through the trench such that side portions of the fin channel remain intact; and forming a doped epitaxial top source and drain region over the fin channel. Methods not requiring a nitride liner and VFET formed using the present techniques are also provided.

公开(公告)号：US10170591B2

公开(公告)日：2019-01-01

申请号：US15178871

申请日：2016-06-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Cheng Chi ,  Fee Li Lie ,  Chi-Chun Liu ,  Ruilong Xie

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/033 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8234

Abstract: A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin.

公开(公告)号：US10170585B2

公开(公告)日：2019-01-01

申请号：US15437840

申请日：2017-02-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Cheng Chi ,  Ruilong Xie

IPC: H01L21/285 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/3105

Abstract: A method is presented for forming equal thickness gate spacers for a CMOS (complementary metal oxide semiconductor) device, the method includes forming a PFET (p-type field effect transistor) device and an NFET (n-type field effect transistor) device each including gate masks formed over dummy gates, forming PFET epi growth regions between the dummy gates of the PFET device, forming NFET epi growth regions between the dummy gates of the NFET device, depositing a nitride liner and an oxide over the PFET and NFET epi growth regions, the nitride liner and oxide extending up to the gate masks, and removing the dummy gates and the gate masks to form HKMGs (high-k metal gates) between the PFET and NFET epi growth regions.

公开(公告)号：US10170582B1

公开(公告)日：2019-01-01

申请号：US15703105

申请日：2017-09-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael P. Belyansky ,  Cheng Chi ,  Ekmini Anuja De Silva ,  Tenko Yamashita

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/033 ,  H01L21/02

Abstract: A method of forming a semiconductor structure includes forming a protective liner comprising a metal oxide above and in direct contact with a semiconductor substrate, a fin extending upward from the semiconductor substrate and a NON hardmask positioned on top of the fin, removing the protective liner from top surfaces of the semiconductor substrate and NON hardmask, the protective liner remaining on sidewalls of the fin and the NON hardmask, depositing a first dielectric layer, simultaneously removing top portions of the first dielectric layer and NON hardmask, the first dielectric layer remains in direct contact with a bottom portion of the protective liner and the semiconductor substrate, removing the protective liner, the removing of the protective liner creates an opening between the first dielectric layer and the bottom portion of the fin that is subsequently filled with a second dielectric layer.

公开(公告)号：US10157827B2

公开(公告)日：2018-12-18

申请号：US15196371

申请日：2016-06-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Cheng Chi ,  Ruilong Xie

IPC: H01L23/522 ,  H01L29/417 ,  H01L23/528 ,  H01L23/485 ,  H01L21/8238 ,  H01L21/311 ,  H01L27/12 ,  H01L29/66

Abstract: A method for forming a semiconductor device comprises forming a gate stack on a channel region of a semiconductor, forming a source/drain region adjacent to the channel region, depositing a first insulator layer over the source/drain region, and removing a portion of the first insulator layer to form a first cavity that exposes a portion of the source/drain region. A first conductive material is deposited in the first cavity, and a conductive extension is formed from the first conductive material over the first insulator layer. A protective layer is deposited over the extension and a second insulator layer is deposited over the protective layer. A portion of the second insulator layer is removed to form a second cavity that exposes the protective layer, and an exposed portion of the protective layer is removed to expose a portion of the extension. A second conductive material is deposited in the second cavity.

公开(公告)号：US20180331217A1

公开(公告)日：2018-11-15

申请号：US16046178

申请日：2018-07-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cheng Chi ,  Tenko Yamashita ,  Chen Zhang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/161

CPC classification number: H01L29/7827 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823481 ,  H01L21/823487 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7856 ,  H01L29/78642

Abstract: A method of forming a vertical transport fin field effect transistor and a long-channel field effect transistor on the same substrate, including, forming a recessed region in a substrate and a fin region adjacent to the recessed region, forming one or more vertical fins on the fin region, forming a long-channel pillar from the substrate in the recessed region, where the long-channel pillar is at a different elevation than the one or more vertical fins, forming two or more long-channel source/drain plugs on the long-channel pillar, forming a bottom source/drain plug in the fin region, where the bottom source/drain plug is below the one or more vertical fins, forming a gate structure on the long-channel pillar and a gate structure on the one or more vertical fins, and forming a top source/drain on the top surface of the one or more vertical fins.

公开(公告)号：US20180240889A1

公开(公告)日：2018-08-23

申请号：US15437840

申请日：2017-02-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Cheng Chi ,  Ruilong Xie

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/3105

CPC classification number: H01L29/6656 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/823425 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/66545

Abstract: A method is presented for forming equal thickness gate spacers for a CMOS (complementary metal oxide semiconductor) device, the method includes forming a PFET (p-type field effect transistor) device and an NFET (n-type field effect transistor) device each including gate masks formed over dummy gates, forming PFET epi growth regions between the dummy gates of the PFET device, forming NFET epi growth regions between the dummy gates of the NFET device, depositing a nitride liner and an oxide over the PFET and NFET epi growth regions, the nitride liner and oxide extending up to the gate masks, and removing the dummy gates and the gate masks to form HKMGs (high-k metal gates) between the PFET and NFET epi growth regions.

公开(公告)号：US20180240873A1

公开(公告)日：2018-08-23

申请号：US15438114

申请日：2017-02-21

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Cheng Chi ,  Chi-Chun Liu ,  Ruilong Xie ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/7827

Abstract: Techniques for VFET top source and drain epitaxy are provided. In one aspect, a method of forming a VFET includes: patterning a fin to form a bottom source/drain region and a fin channel of the VFET; forming bottom spacers on the bottom source/drain region; depositing a high-κ gate dielectric onto the bottom spacers and along sidewalls of the fin channel; forming gates over the bottom spacers; forming top spacers on the gates; partially recessing the fin channel to create a trench between the top spacers; forming a nitride liner along sidewalls of the trench; fully recessing the fin channel through the trench such that side portions of the fin channel remain intact; and forming a doped epitaxial top source and drain region over the fin channel. Methods not requiring a nitride liner and VFET formed using the present techniques are also provided.

公开(公告)号：US20180174855A1

公开(公告)日：2018-06-21

申请号：US15890859

申请日：2018-02-07

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Cheng Chi ,  Fee Li Lie ,  Chi-Chun Liu ,  Ruilong Xie

IPC: H01L21/308 ,  H01L21/8234 ,  H01L21/311

CPC classification number: H01L21/3086 ,  H01L21/0271 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0603 ,  H01L29/0692

Abstract: A method of making a semiconductor device includes disposing a first hard mask (HM), amorphous silicon, and second HM on a substrate; disposing oxide and neutral layers on the second HM; removing a portion of the oxide and neutral layers to expose a portion of the second HM; forming a guiding pattern by selectively backfilling with a polymer; forming a self-assembled block copolymer (BCP) on the guiding pattern; removing a portion of the BCP to form an etch template; transferring the pattern from said template into the substrate and forming uniform silicon fin arrays with two types of HM stacks with different materials and heights; gap-filling with oxide followed by planarization; selectively removing and replacing the taller HM stack with a third HM material; planarizing the surface and exposing both HM stacks; and selectively removing the shorter HM stack and the silicon fins underneath.

公开(公告)号：US09984920B2

公开(公告)日：2018-05-29

申请号：US15206789

申请日：2016-07-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hsueh-Chung Chen ,  Cheng Chi ,  Lin Hu ,  Kafai Lai ,  Chi-Chun Liu ,  Jed W. Pitera

IPC: G06F17/50 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L21/02

CPC classification number: H01L21/76816 ,  G06F17/5072 ,  H01L21/02118 ,  H01L21/02318 ,  H01L23/5226 ,  H01L23/528

Abstract: A method for local pattern density control of a device layout used by graphoepitaxy directed self-assembly (DSA) processes includes importing a multi-layer semiconductor device design into an assist feature system and determining overlapping regions between two or more layers in the multi-layer semiconductor device design using at least one Boolean operation. A fill for assist features is generated to provide dimensional consistency of device features by employing the overlapping regions to provide placement of the assist features. An updated device layout is stored in a memory device.