公开(公告)号：US20220181439A1

公开(公告)日：2022-06-09

申请号：US17677007

申请日：2022-02-22

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Dechao Guo ,  Ruqiang Bao ,  Junli Wang ,  Lan Yu ,  Reinaldo Vega ,  Adra Carr

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/08

Abstract: Techniques are provided to fabricate semiconductor devices having a nanosheet field-effect transistor device disposed on a semiconductor substrate. The nanosheet field-effect transistor device includes a nanosheet stack structure including a semiconductor channel layer and a source/drain region in contact with an end portion of the semiconductor channel layer of the nanosheet stack structure. A trench formed in the source/drain region is filled with a metal-based material. The metal-based material filling the trench in the source/drain region mitigates the effect of source/drain material overfill on the contact resistance of the semiconductor device.

公开(公告)号：US11289573B2

公开(公告)日：2022-03-29

申请号：US16290611

申请日：2019-03-01

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Dechao Guo ,  Ruqiang Bao ,  Junli Wang ,  Lan Yu ,  Reinaldo Vega ,  Adra Carr

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/08

Abstract: Techniques are provided to fabricate semiconductor devices having a nanosheet field-effect transistor device disposed on a semiconductor substrate. The nanosheet field-effect transistor device includes a nanosheet stack structure including a semiconductor channel layer and a source/drain region in contact with an end portion of the semiconductor channel layer of the nanosheet stack structure. A trench formed in the source/drain region is filled with a metal-based material. The metal-based material filling the trench in the source/drain region mitigates the effect of source/drain material overfill on the contact resistance of the semiconductor device.

公开(公告)号：US20210098698A1

公开(公告)日：2021-04-01

申请号：US16587543

申请日：2019-09-30

Applicant: International Business Machines Corporation

Inventor： Reinaldo Vega ,  Takashi Ando ,  Jianshi Tang ,  Praneet Adusumilli

IPC: H01L45/00

Abstract: Tapered resistive memory devices with interface dipoles are provided. In one aspect, a ReRAM device includes: a bottom electrode; a core dielectric that is thermally conductive disposed on the bottom electrode; an oxide resistive memory cell disposed along outer sidewalls of the core dielectric, wherein the oxide resistive memory cell has inner edges adjacent to the core dielectric, and outer edges that are tapered; an outer coating disposed adjacent to the outer edges of the oxide resistive memory cell; and a top electrode disposed on the core dielectric, the oxide resistive memory cell, and the outer coating. A method of forming a ReRAM device as well as a method of operating a ReRAM device are also provided.

公开(公告)号：US10885979B2

公开(公告)日：2021-01-05

申请号：US16379250

申请日：2019-04-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jianshi Tang ,  Praneet Adusumilli ,  Reinaldo Vega ,  Takashi Ando

IPC: G11C11/00 ,  G11C13/02 ,  G11C11/56 ,  G11C13/00

Abstract: A method is presented for mitigating conductance drift in intercalation cells for neuromorphic computing. The method includes forming a first electro-chemical random access memory (ECRAM) structure over a substrate and forming a second ECRAM over the substrate, the first and second ECRAMs sharing a common contact. The common contact can be either a source contact or a drain contact. Each of the first and second ECRAMs can include a tungsten oxide layer, an electrolyte layer, and a gate contact.

公开(公告)号：US10833048B2

公开(公告)日：2020-11-10

申请号：US15950239

申请日：2018-04-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Li-Wen Hung ,  Reinaldo Vega ,  Hari Mallela

IPC: H01L23/00

Abstract: A technique relates to a semiconductor device. First nanowires are formed on a first substrate, the first nanowires being electrically coupled to one or more first electrical sites on the first substrate. Second nanowires are formed on a second substrate, the second nanowires being electrically coupled to one or more second electrical sites on the second substrate. The first nanowires and the second nanowires are electrically coupled such that the one or more first electrical sites are electrically coupled to the one or more second electrical sites.

公开(公告)号：US20200284823A1

公开(公告)日：2020-09-10

申请号：US16291755

申请日：2019-03-04

Applicant: International Business Machines Corporation

Inventor： Kushagra Sinha ,  Pablo Nieves ,  Reinaldo Vega

IPC: G01R1/073

Abstract: A test probe assembly for use in testing a semiconductor wafer includes a probe card, a plurality of test probes mounted to the probe card and one or more piezoelectric elements mounted to each test probe. The piezoelectric elements are configured to move respective probe ends of the individual test probes in at least one direction to facilitate realignment of the probe ends for semiconductor wafer testing.

公开(公告)号：US20200258995A1

公开(公告)日：2020-08-13

申请号：US16745100

申请日：2020-04-22

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Michael A. Guillorn ,  Terence Hook ,  Robert R. Robison ,  Reinaldo Vega ,  Tenko Yamashita

IPC: H01L29/423 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/775 ,  H01L29/06 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78

Abstract: One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.

公开(公告)号：US20200251568A1

公开(公告)日：2020-08-06

申请号：US16745049

申请日：2020-01-16

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Michael A. Guillorn ,  Terence Hook ,  Robert R. Robison ,  Reinaldo Vega ,  Tenko Yamashita

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L29/06 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/786

Abstract: One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.

公开(公告)号：US10658224B2

公开(公告)日：2020-05-19

申请号：US16126621

申请日：2018-09-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Huimei Zhou ,  Gen Tsutsui ,  Veeraraghavan S. Basker ,  Andrew M. Greene ,  Dechao Guo ,  Huiming Bu ,  Reinaldo Vega

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66 ,  H01L29/78 ,  H01L21/32

Abstract: Integrated chips and methods of forming the same include oxidizing a portion of a semiconductor fin, which includes a channel layer and an intermediate semiconductor layer, to electrically isolate active regions of the semiconductor fin by forming an oxide that fully penetrates the channel layer and the intermediate semiconductor layer. A semiconductor device is formed on each of the active regions.

公开(公告)号：US09859384B2

公开(公告)日：2018-01-02

申请号：US15431807

申请日：2017-02-14

Applicant: International Business Machines Corporation

Inventor： Hari V. Mallela ,  Robert R. Robison ,  Reinaldo Vega ,  Rajasekhar Venigalla

IPC: H01L21/00 ,  H01L21/338 ,  H01L21/337 ,  H01L21/8238 ,  H01L21/336 ,  H01L29/80 ,  H01L29/94 ,  H01L29/417 ,  H01L29/78 ,  H01L23/485

CPC classification number: H01L29/41741 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823885 ,  H01L23/485 ,  H01L27/092 ,  H01L29/0676 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78687 ,  H01L29/78696

Abstract: Semiconductor devices having vertical FET (field effect transistor) devices with metallic source/drain regions are provided, as well as methods for fabricating such vertical FET devices. For example, a semiconductor device includes a first source/drain region formed on a semiconductor substrate, a vertical semiconductor fin formed on the first source/drain region, a second source/drain region formed on an upper surface of the vertical semiconductor fin, a gate structure formed on a sidewall surface of the vertical semiconductor fin, and an insulating material that encapsulates the vertical semiconductor fin and the gate structure. The first source/drain region comprises a metallic layer and at least a first epitaxial semiconductor layer. For example, the metallic layer of the first source/drain region comprises a metal-semiconductor alloy such as silicide.