公开(公告)号：US10262861B2

公开(公告)日：2019-04-16

申请号：US15632984

申请日：2017-06-26

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Juntao Li ,  Peng Xu

IPC: H01L21/033 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/308 ,  H01L29/78 ,  H01L29/165

Abstract: A method of fabricating a hard mask structure is provided. According to the method, a hard mask layer is disposed over a substrate. The hard mask layer includes a lower hard mask layer disposed over the substrate and an upper hard mask layer disposed over the lower hard mask layer. The hard mask layer is patterned and the upper hard mask layer is removed by selectively etching the upper hard mask layer until reaching the lower hard mask layer to form a top portion of the hard mask structure having a first dimension. A spacer material is disposed on a sidewall of the top portion of the hard mask structure. The lower hard mask layer is removed by selectively etching the lower mask layer until reaching the substrate to form a bottom portion of the hard mask structure having a second dimension.

公开(公告)号：US10134859B1

公开(公告)日：2018-11-20

申请号：US15808869

申请日：2017-11-09

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Heng Wu ,  Peng Xu

IPC: H01L21/335 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/08

Abstract: A field-effect transistor device including an asymmetric spacer assembly allows lower parasitic capacitance on the drain side of the device and lower resistance on the source side. The asymmetric spacer assembly is formed by a self-aligned process, resulting in less gate/junction overlap on the drain side of the device and greater gate/junction overlap on the source side of the device. Asymmetric transistors having small gate lengths can be obtained without overlay/misalignment issues.

公开(公告)号：US20180277630A1

公开(公告)日：2018-09-27

申请号：US15805700

申请日：2017-11-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Juntao Li ,  Peng Xu

IPC: H01L29/06 ,  H01L21/324 ,  H01L21/28 ,  H01L21/02 ,  H01L25/00 ,  H01L25/07 ,  H01L29/08

CPC classification number: H01L29/0684 ,  H01L21/28255 ,  H01L21/324 ,  H01L25/07 ,  H01L25/50 ,  H01L29/0843

Abstract: Methods of forming integrated chips include forming a respective stack of sheets in two regions, each stack having first layers and second layers. The second layers are etched away in the first region. The second region is annealed to change the composition of the first layers in the second region by interaction with the second layers in the second region. A gate stack is formed in the first and second region.

公开(公告)号：US10079229B1

公开(公告)日：2018-09-18

申请号：US15495197

申请日：2017-04-24

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Juntao Li ,  Peng Xu

IPC: H01L21/20 ,  H01L27/06 ,  H01L49/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/3205 ,  H01L29/78 ,  H01L29/06

Abstract: A technique relates to forming resistor fins on a substrate. A shallow trench isolation material is formed on dummy fins and the substrate, and the dummy fins are formed on the substrate. Predefined ones of the dummy fins are removed, thereby forming voids in the shallow trench isolation material corresponding to previous locations of the predefined ones of the dummy fins. A first material is deposited into the voids. The height of the first material is reduced, thereby forming trenches in the shallow trench isolation material. A second material is deposited into the trenches to be on top of the first material, thereby forming the resistor fins of a resistor device. A metal contact layer is formed so as to contact a top surface of the first material at predefined locations.

公开(公告)号：US20180240714A1

公开(公告)日：2018-08-23

申请号：US15811821

申请日：2017-11-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Peng Xu ,  Jie Yang

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/36 ,  H01L21/306 ,  H01L27/092 ,  H01L21/308

Abstract: A method of making a semiconductor device including forming a first blanket layer on a substrate; forming a second blanket layer on the first blanket layer; patterning a first fin of a first transistor region and a second fin of a second transistor region in the first blanket layer and the second blanket layer; depositing a mask on the second transistor region; removing the first fin to form a trench; growing a first semiconductor layer in the trench where the first fin was removed; and growing a second semiconductor layer on the first semiconductor layer.

公开(公告)号：US20180240713A1

公开(公告)日：2018-08-23

申请号：US15435627

申请日：2017-02-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Peng Xu ,  Jie Yang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/306 ,  H01L21/308 ,  H01L29/36 ,  H01L29/78 ,  H01L29/66

Abstract: A method of making a semiconductor device including forming a first blanket layer on a substrate; forming a second blanket layer on the first blanket layer; patterning a first fin of a first transistor region and a second fin of a second transistor region in the first blanket layer and the second blanket layer; depositing a mask on the second transistor region; removing the first fin to form a trench; growing a first semiconductor layer in the trench where the first fin was removed; and growing a second semiconductor layer on the first semiconductor layer.

公开(公告)号：US10032858B2

公开(公告)日：2018-07-24

申请号：US15477351

申请日：2017-04-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Dongbing Shao ,  Zheng Xu

IPC: H01L21/00 ,  H01L49/02

Abstract: A capacitive device includes a first electrode comprising a nanosheet stack and a second electrode comprising a nanosheet stack, the second electrode arranged substantially parallel to the first electrode. A first conductive contact is arranged on a basal end of the first electrode, and a second conductive contact is arranged on a basal end of the second electrode.

公开(公告)号：US10032856B1

公开(公告)日：2018-07-24

申请号：US15414011

申请日：2017-01-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Zhenxing Bi ,  Kangguo Cheng ,  Zheng Xu

IPC: H01L21/8242 ,  H01L49/02 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324 ,  H01L21/283 ,  H01L21/311 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/06

Abstract: A capacitive device includes a first electrode comprising a nanosheet stack, and a second electrode comprising a nanosheet stack, the second electrode arranged substantially parallel to the first electrode. A first conductive contact is arranged on a basal end of the first electrode, and a second conductive contact arranged on a basal end of the second electrode.

公开(公告)号：US09991328B2

公开(公告)日：2018-06-05

申请号：US15246912

申请日：2016-08-25

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Wei Wang ,  Zheng Xu

IPC: H01L49/02 ,  H01L21/324 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/3105

CPC classification number: H01L28/20 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/0259 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/31051 ,  H01L21/324

Abstract: A method of forming an integrated circuit device having a nanosheet resistor includes forming a nanosheet structure having alternating sheets of silicon and silicon germanium. An ion implantation is performed on the nanosheet structure. A thermal anneal is performed on the nanosheet structure. A dielectric oxide is placed around the nanosheet structure. A first contact and a second contact are coupled to the nanosheet structure to form a resistor between the first contact and the second contact. Other embodiments are also described herein.

公开(公告)号：US09972542B1

公开(公告)日：2018-05-15

申请号：US15398232

申请日：2017-01-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Peng Xu ,  Wenyu Xu

IPC: H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L21/823807 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6681 ,  H01L29/775

Abstract: Semiconductor devices and methods of forming the same include forming stacks of alternating layers of first channel material and second channel material in a first device region and a second device region. A first layer cap is formed at ends of the layers of first channel material. A second layer cap is formed at ends of the layers of second channel material. The first layer caps are etched away in the first device region. The second layer caps are etched away in the second device region. First source/drain regions are grown in the first device region from exposed ends of the layers of the first channel material. Second source/drain regions are grown in the second device region from exposed ends of the layers of the second channel material.