公开(公告)号：US20190198520A1

公开(公告)日：2019-06-27

申请号：US15948639

申请日：2018-04-09

Applicant: Micron Technology, Inc.

Inventor： Changhan Kim ,  Chet E. Carter ,  Cole Smith ,  Collin Howder ,  Richard J. Hill ,  Jie Li

IPC: H01L27/11582 ,  H01L29/10 ,  H01L23/528 ,  H01L27/11568 ,  H01L29/51 ,  H01L29/49 ,  H01L21/311 ,  H01L21/02 ,  H01L21/28 ,  H01L27/11521 ,  H01L27/11556 ,  H01L29/788 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L27/11582 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02636 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L23/528 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/1037 ,  H01L29/4991 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7883 ,  H01L29/7889 ,  H01L29/7926

Abstract: Some embodiments include a method of forming an assembly (e.g., a memory array). A first opening is formed through a stack of alternating first and second levels. The first levels contain silicon nitride, and the second levels contain silicon dioxide. Some of the silicon dioxide of the second levels is replaced with memory cell structures. The memory cell structures include charge-storage regions adjacent charge-blocking regions. Tunneling material is formed within the first opening, and channel material is formed adjacent the tunneling material. A second opening is formed through the stack. The second opening extends through remaining portions of the silicon dioxide, and through the silicon nitride. The remaining portions of the silicon dioxide are removed to form cavities. Conductive regions are formed within the cavities. The silicon nitride is removed to form voids between the conductive regions. Some embodiments include memory arrays.

公开(公告)号：US10304853B2

公开(公告)日：2019-05-28

申请号：US16031919

申请日：2018-07-10

Applicant: Micron Technology, Inc.

Inventor： David Daycock ,  Richard J. Hill ,  Christopher Larsen ,  Woohee Kim ,  Justin B. Dorhout ,  Brett D. Lowe ,  John D. Hopkins ,  Qian Tao ,  Barbara L. Casey

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/423 ,  H01L29/10 ,  H01L21/28 ,  H01L29/792

Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels and not along the insulative levels. The charge-trapping material is spaced from the control gate regions by charge-blocking material. Channel material extends vertically along the stack and is laterally spaced from the charge-trapping material by dielectric material. Some embodiments include methods of forming NAND memory arrays.

公开(公告)号：US20180315771A1

公开(公告)日：2018-11-01

申请号：US15975893

申请日：2018-05-10

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Richard J. Hill ,  John A. Smythe

IPC: H01L27/11582 ,  H01L21/28 ,  H01L27/11556 ,  H01L21/306 ,  H01L21/02 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L27/11582 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/28282 ,  H01L29/1037 ,  H01L29/66545

Abstract: An array of elevationally-extending strings of memory cells comprises a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control-gate regions. Charge-storage material of individual memory cells extend elevationally along individual of the control-gate regions of the wordline levels and do not extend elevationally along the insulative levels. A charge-blocking region of the individual memory cells extends elevationally along the individual control-gate regions of the wordline levels laterally through which charge migration between the individual control-gate regions and the charge-storage material is blocked. Channel material extends elevationally along the stack and is laterally spaced from the charge-storage material by insulative charge-passage material. All of the charge-storage material of individual of the elevationally-extending strings of memory cells is laterally outward of all of the insulative charge-passage material of the individual elevationally-extending strings of memory cells. Other embodiments, including method embodiments, are disclosed.

公开(公告)号：US20250107204A1

公开(公告)日：2025-03-27

申请号：US18974584

申请日：2024-12-09

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Richard J. Hill ,  Indra V. Chary ,  Lars P. Heineck

IPC: H01L29/417 ,  H01L21/768 ,  H01L23/528 ,  H01L29/40

Abstract: Microelectronic devices include a tiered stack having vertically alternating insulative and conductive structures. A first series of stadiums is defined in the tiered stack within a first block of a dual-block structure. A second series of stadiums is defined in the tiered stack within a second block of the dual-block structure. The first and second series of stadiums are substantially symmetrically structured about a trench at a center of the dual-block structure. The trench extends a width of the first and second series of stadiums. The stadiums of the first and second series of stadiums have opposing staircase structures comprising steps at ends of the conductive structures of the tiered stack. Conductive source/drain contact structures are in the stack and extend substantially vertically from a source/drain region at a floor of the trench. Additional microelectronic devices are also disclosed, as are methods of fabrication and electronic systems.

公开(公告)号：US12237259B2

公开(公告)日：2025-02-25

申请号：US17443531

申请日：2021-07-27

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  Harsh Narendrakumar Jain ,  Naveen Kaushik ,  Adam L. Olson ,  Richard J. Hill ,  Lars P. Heineck

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H10B41/35 ,  H10B43/35

Abstract: An electronic device comprising multilevel bitlines comprising first bitlines and second bitlines. The first bitlines and the second bitlines are positioned at different levels. Pillar contacts are electrically connected to the first bitlines and to the second bitlines. Level 1 contacts are electrically connected to the first bitlines and level 2 contacts are electrically connected to the second bitlines. A liner is between the first bitlines and the level 2 contacts. Each bitline of the first bitlines is electrically connected to a single pillar contact in a subblock adjacent to the level 1 contacts and each bitline of the second bitlines is electrically connected to a single pillar contact adjacent to the level 2 contacts. Methods of forming an electronic device and related systems are also disclosed.

公开(公告)号：US12191249B2

公开(公告)日：2025-01-07

申请号：US17446868

申请日：2021-09-03

Applicant: Micron Technology, Inc.

Inventor： David H. Wells ,  Richard J. Hill ,  Umberto M. Meotto ,  Matthew Thorum

IPC: H10B43/10 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  G11C16/04

Abstract: A microelectronic device comprises a stack structure overlying a source tier. The stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The microelectronic device comprises a staircase structure within the stack structure and having steps comprising lateral edges of the tiers, support structures vertically extending through the stack structure and within a horizontal area of the staircase structure, and conductive contacts vertically extending through the stack structure and horizontally neighboring the support structures within the horizontal area of the staircase structure. Each of the conductive contacts has a horizontally projecting portion in contact with one of the conductive structures of the stack structure at one of the steps of the staircase structure. Related memory devices, electronic systems, and methods of forming the microelectronic devices are also described.

公开(公告)号：US12166094B2

公开(公告)日：2024-12-10

申请号：US17373258

申请日：2021-07-12

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Richard J. Hill ,  Indra V. Chary ,  Lars P. Heineck

IPC: H01L29/417 ,  H01L21/768 ,  H01L23/528 ,  H01L29/40

Abstract: Microelectronic devices include a tiered stack having vertically alternating insulative and conductive structures. A first series of stadiums is defined in the tiered stack within a first block of a dual-block structure. A second series of stadiums is defined in the tiered stack within a second block of the dual-block structure. The first and second series of stadiums are substantially symmetrically structured about a trench at a center of the dual-block structure. The trench extends a width of the first and second series of stadiums. The stadiums of the first and second series of stadiums have opposing staircase structures comprising steps at ends of the conductive structures of the tiered stack. Conductive source/drain contact structures are in the stack and extend substantially vertically from a source/drain region at a floor of the trench. Additional microelectronic devices are also disclosed, as are methods of fabrication and electronic systems.

公开(公告)号：US20240395326A1

公开(公告)日：2024-11-28

申请号：US18652288

申请日：2024-05-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Paolo Tessariol ,  Richard J. Hill ,  Aaron S. Yip ,  Kunal Parekh

IPC: G11C16/04 ,  G11C5/06 ,  H01L29/788 ,  H01L29/792 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: Memory array structures might include a data line, a common source, and a plurality of sub-blocks of memory cells selectively connected to the data line and to the common source. Sub-blocks of memory cells might include memory cells formed to be around channel material structures, and might include isolation of source-side select lines of adjacent sub-blocks of memory cells. Methods are included for forming such memory array structures.

公开(公告)号：US20240162325A1

公开(公告)日：2024-05-16

申请号：US18421820

申请日：2024-01-24

Applicant: Micron Technology, Inc.

Inventor： Michael A. Lindemann ,  Collin Howder ,  Yoshiaki Fukuzumi ,  Richard J. Hill

IPC: H01L29/45 ,  H01L21/28 ,  H01L29/417 ,  H01L29/792 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L29/458 ,  H01L29/40117 ,  H01L29/41725 ,  H01L29/792 ,  H10B43/27 ,  H10B43/35

Abstract: Electronic devices comprising a doped dielectric material adjacent to a source contact, tiers of alternating conductive materials and dielectric materials adjacent to the doped dielectric material, and pillars extending through the tiers, the doped dielectric material, and the source contact and into the source stack. Related methods and electronic systems are also disclosed.

公开(公告)号：US20240121943A1

公开(公告)日：2024-04-11

申请号：US18545180

申请日：2023-12-19

Applicant: Micron Technology, Inc.

Inventor： David K. Hwang ,  Richard J. Hill ,  Gurtej S. Sandhu

IPC: H10B12/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H10B12/315 ,  H01L29/0684 ,  H01L29/42356 ,  H01L29/66666 ,  H01L29/7827 ,  H10B12/0335 ,  H10B12/482 ,  H10B12/488

Abstract: Some embodiments include an integrated assembly having first conductive structures extending along a first direction. Spaced-apart upwardly-opening container-shapes are over the first conductive structures. Each of the container-shapes has a first sidewall region, a second sidewall region, and a bottom region extending from the first sidewall region to the second sidewall region. Each of the first and second sidewall regions includes a lower source/drain region, an upper source/drain region, and a channel region between the upper and lower source/drain regions. The lower source/drain regions are electrically coupled with the first conductive structures. Second conductive structures extend along a second direction which crosses the first direction. The second conductive structures have gate regions operatively adjacent the channel regions. Storage elements are electrically coupled with the upper source/drain regions. Some embodiments include methods of forming integrated assemblies.