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    Adaptation to 3-phase signal swap within a trio
    93.
    发明授权
    Adaptation to 3-phase signal swap within a trio 有权

    公开(公告)号：US09621333B2

    公开(公告)日：2017-04-11

    申请号：US15270853

    申请日：2016-09-20

    Applicant: QUALCOMM Incorporated

    Inventor： George Alan Wiley ,  Ohjoon Kwon

    IPC: H04L7/00 ,  H04L27/20 ,  H04L27/227 ,  H04L27/00 ,  H04B1/40

    CPC classification number: H04L7/0087 ,  H04B1/40 ,  H04L7/0083 ,  H04L25/14 ,  H04L25/4923 ,  H04L27/0002 ,  H04L27/20 ,  H04L27/227

    Abstract: Systems, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Two Integrated Circuit (IC) devices may be collocated in an electronic apparatus and communicatively coupled through a 3-wire, 3-phase interface. A data transfer method operational on a first of the two or more devices includes determining presence of a misalignment of the 3-wire communication link involving two or more wires, and inverting a first bit of a 3-bit symbol encoded in a transition of signaling state of the 3-wire communication link when the misalignment of the 3-wire communication link is determined to affect phase relationships between two or more signals carried on the three wires, such that inverting the first bit corrects the phase relationships between the two or more signals. A version of the 3-phase signal may be communicated in a different phase state through each of three wires.

    REDUCING TRANSMITTER ENCODING JITTER IN A C-PHY INTERFACE USING MULTIPLE CLOCK PHASES TO LAUNCH SYMBOLS
    94.
    发明申请
    REDUCING TRANSMITTER ENCODING JITTER IN A C-PHY INTERFACE USING MULTIPLE CLOCK PHASES TO LAUNCH SYMBOLS 审中-公开
    在使用多个时钟相位启动符号的C-PHY接口中减少发射机编码抖动

    公开(公告)号：US20170039163A1

    公开(公告)日：2017-02-09

    申请号：US15332756

    申请日：2016-10-24

    Applicant: QUALCOMM Incorporated

    Inventor： Dhaval Sejpal ,  Shih-Wei Chou ,  Chulkyu Lee ,  Ohjoon Kwon ,  George Alan Wiley

    IPC: G06F13/42

    CPC classification number: G06F13/4291 ,  G06F13/4278 ,  H04L25/4917

    Abstract: Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. One method includes providing a plurality of launch clock signals, including launch clock signals having a different phase shifts, determining a type of transition in signaling state that will occur on each wire of the 3-wire interface at a boundary between two consecutively transmitted symbols, and selecting one of the plurality of launch clock signals to initiate the transition of signaling state on each wire of the 3-phase interface. Selecting one of the plurality of launch clock signals may include selecting a first launch clock signal when the transition in signaling state terminates at an undriven state, and selecting a second launch clock signal when the transition in signaling state begins at an undriven state. An edge in the first launch clock signal may occur before a corresponding edge in the second launch clock signal.

    Abstract translation: 公开了用于在多线接口上的传输中的错误检测的装置，系统和方法。 一种方法包括提供多个发射时钟信号，包括具有不同相移的发射时钟信号，确定将在两条连续发射的符号之间的边界处在3线接口的每条线路上发生的信令状态的转换类型， 以及选择所述多个发射时钟信号之一以启动所述三相接口的每条线路上的信令状态的转换。 选择多个发射时钟信号中的一个可以包括当信令状态的转换在未驱动状态下终止时选择第一发射时钟信号，以及当信令状态的转变在未驱动状态开始时选择第二发射时钟信号。 第一个启动时钟信号中的边沿可能发生在第二个启动时钟信号的相应边沿之前。

    Camera control interface extension bus
    95.
    发明授权
    Camera control interface extension bus 有权
    相机控制接口扩展总线

    公开(公告)号：US09552325B2

    公开(公告)日：2017-01-24

    申请号：US14302362

    申请日：2014-06-11

    Applicant: QUALCOMM Incorporated

    Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Joseph Cheung

    IPC: G06F13/42 ,  G06F13/364 ,  H04L7/033

    CPC classification number: G06F13/4291 ,  G06F13/364 ,  G06F13/4282 ,  G06F13/4295 ,  H04L7/0331

    Abstract: System, methods and apparatus are described that offer improved performance of a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. CCI extension (CCIe) devices are described. CCIe devices may be configured as a bus master or as a slave. In one method, a CCIe transmitter may generate a transition number from a set of bits, convert the transition number into a sequence of symbols, and transmit the sequence of symbols in the signaling state of a two-wire serial bus. Timing information may be encoded in the transitions between symbols of consecutive pairs of symbols in the sequence of symbols. For example, each transition may cause a change in the signaling state of at least one wire of the two-wire serial bus. A CCIe receiver may derive a receive clock from the transitions in order to receive and decode the sequence of symbols.

    Abstract translation: 描述了提供用于内部集成电路（I2C）和/或相机控制接口（CCI）操作的串行总线的改进的性能的系统，方法和装置。 描述CCI扩展（CCIe）设备。 CCIe设备可以配置为总线主机或从机。 在一种方法中，CCIe发射机可以从一组比特生成转换号码，将转换号码转换为符号序列，并以两线串行总线的信令状态发送符号序列。 定时信息可以在符号序列中的连续符号对符号之间的转换中被编码。 例如，每个转换可能导致两线串行总线的至少一根线的信令状态改变。 CCIe接收机可以从转换中导出接收时钟，以便接收和解码符号序列。

    LOW-POWER MODE SIGNAL BRIDGE FOR OPTICAL MEDIA
    96.
    发明申请
    LOW-POWER MODE SIGNAL BRIDGE FOR OPTICAL MEDIA 有权
    用于光媒体的低功耗模式信号桥

    公开(公告)号：US20170019186A1

    公开(公告)日：2017-01-19

    申请号：US14802408

    申请日：2015-07-17

    Applicant: QUALCOMM Incorporated

    Inventor： George Alan Wiley

    IPC: H04B10/80 ,  H04L29/06

    CPC classification number: H04B10/801 ,  G06F13/387 ,  G06F13/4045 ,  H04L69/08 ,  H04L69/18 ,  Y02D10/14 ,  Y02D10/151

    Abstract: System, methods and apparatus are described that facilitate transmission of data between two devices. A data transfer method includes receiving first data from a first interface, the first data being received in signaling transmitted by a first device according to a first protocol, determining a mode of operation for a communication link to be used for transmitting the first data to a second device, transmitting the first data to the second device over an optical path of the communication link in a first mode of operation, transmitting the first data in accordance with the first protocol to the second device over an electrical path of the communication link in a second mode of operation, and in a third mode of operation, translating the first data to obtain second data, and transmitting the second data in accordance with a second protocol to the second device over the electrical path.

    Abstract translation: 描述了促进两个设备之间的数据传输的系统，方法和装置。 数据传输方法包括从第一接口接收第一数据，第一数据是按照第一协议由第一设备发送的信令中接收的，确定用于将第一数据发送到第一数据的通信链路的操作模式 第二设备，以第一操作模式通过通信链路的光路将第一数据发送到第二设备，根据第一协议，通过通信链路的电路径将第一数据发送到第二设备 第二操作模式，并且在第三操作模式中，转换第一数据以获得第二数据，以及根据第二协议将第二数据通过电路径发送到第二设备。

    Multi-wire signaling with matched propagation delay among wire pairs
    97.
    发明授权
    Multi-wire signaling with matched propagation delay among wire pairs 有权
    电线对之间具有匹配传播延迟的多线信号

    公开(公告)号：US09521058B2

    公开(公告)日：2016-12-13

    申请号：US15097027

    申请日：2016-04-12

    Applicant: QUALCOMM Incorporated

    Inventor： Shree Krishna Pandey ,  Arun Chandra Kundu ,  George Alan Wiley ,  Chulkyu Lee

    IPC: H04L25/02 ,  H04L12/26 ,  H04L7/00 ,  H04B3/00 ,  H04B3/462 ,  H04B3/54

    CPC classification number: H04L43/087 ,  G06F13/40 ,  H04B3/00 ,  H04B3/462 ,  H04B3/542 ,  H04L7/0041 ,  H04L25/0264 ,  H04L25/14

    Abstract: In a multi-wire channel that includes at least three wires, each unique wire pair of the multi-wire channel has approximately the same signal propagation time. In this way, jitter can be mitigated in the multi-wire channel for signaling where, for a given data transfer, a differential signal is transmitting on a particular pair of the wires and every other wire is floating. In some implementations, matching of the signal propagation times involves providing additional delay for at least one of the wires. The additional delay is provided using passive signal delay techniques and/or active signal delay techniques.

    Abstract translation: 在包括至少三条线的多线通道中，多线通道的每条独特的线对具有大致相同的信号传播时间。 以这种方式，可以在用于信令的多线信道中减轻抖动，其中对于给定的数据传输，差分信号在特定的一对导线上传输，并且每隔一个线路浮动。 在一些实现中，信号传播时间的匹配涉及为至少一条电线提供额外的延迟。 使用无源信号延迟技术和/或有源信号延迟技术来提供额外的延迟。

    MULTI-WIRE OPEN-DRAIN LINK WITH DATA SYMBOL TRANSITION BASED CLOCKING
    98.
    发明申请
    MULTI-WIRE OPEN-DRAIN LINK WITH DATA SYMBOL TRANSITION BASED CLOCKING 有权
    多线打开链接与数据符号转换的时钟

    公开(公告)号：US20160261400A1

    公开(公告)日：2016-09-08

    申请号：US15156555

    申请日：2016-05-17

    Applicant: QUALCOMM Incorporated

    Inventor： Shoichiro Sengoku ,  Joseph Cheung ,  George Alan Wiley

    IPC: H04L7/00 ,  H04L7/033

    CPC classification number: H04L7/0087 ,  H03K3/017 ,  H03K5/13 ,  H03K5/133 ,  H03K5/134 ,  H03K5/14 ,  H03K5/153 ,  H03K5/1534 ,  H03K19/00 ,  H03K2005/00293 ,  H03L7/081 ,  H04L7/0037 ,  H04L7/033 ,  H04L7/0331

    Abstract: A method, an apparatus, and a computer program product are described. The apparatus generates a receive clock signal for receiving data from a multi-wire open-drain link by determining a transition in a signal received from the multi-wire open-drain link, generating a clock pulse responsive to the transition, delaying the clock pulse by a preconfigured first interval if the transition is in a first direction, and delaying the clock by a preconfigured second interval if the transition is in a second direction. The preconfigured first and/or second intervals are configured based on a rise time and/or a fall time associated with the communication interface and may be calibrated by measuring respective delays associated with clock pulses generated for first and second calibration transitions.

    Abstract translation: 描述了一种方法，装置和计算机程序产品。 该装置通过确定从多线开漏链路接收的信号中的转变来产生用于从多线开漏链路接收数据的接收时钟信号，响应于该转换产生时钟脉冲，延迟时钟脉冲 如果转换处于第一方向，则通过预先配置的第一间隔，并且如果转换处于第二方向，则将时钟延迟预先配置的第二间隔。 基于与通信接口相关联的上升时间和/或下降时间来配置预配置的第一和/或第二间隔，并且可以通过测量与为第一和第二校准转换产生的时钟脉冲相关联的相应延迟来校准预配置的第一和/或第二间隔。

    Multi-wire open-drain link with data symbol transition based clocking
    99.
    发明授权
    Multi-wire open-drain link with data symbol transition based clocking 有权
    多线开漏链路，具有基于数据符号转换的时钟

    公开(公告)号：US09374216B2

    公开(公告)日：2016-06-21

    申请号：US14220056

    申请日：2014-03-19

    Applicant: QUALCOMM Incorporated

    Inventor： Shoichiro Sengoku ,  Joseph Cheung ,  George Alan Wiley

    IPC: H04L7/033 ,  H03K5/1534 ,  H03K3/017 ,  H03K5/153 ,  H03L7/081 ,  H03K5/13 ,  H03K5/134 ,  H03K19/00 ,  H03K5/14 ,  H03K5/00 ,  H04L7/00

    CPC classification number: H04L7/0087 ,  H03K3/017 ,  H03K5/13 ,  H03K5/133 ,  H03K5/134 ,  H03K5/14 ,  H03K5/153 ,  H03K5/1534 ,  H03K19/00 ,  H03K2005/00293 ,  H03L7/081 ,  H04L7/0037 ,  H04L7/033 ,  H04L7/0331

    Abstract: A method, an apparatus, and a computer program product are described. The apparatus generates a receive clock signal for receiving data from a multi-wire open-drain link by determining a transition in a signal received from the multi-wire open-drain link, generating a clock pulse responsive to the transition, delaying the clock pulse by a preconfigured first interval if the transition is in a first direction, and delaying the clock by a preconfigured second interval if the transition is in a second direction. The preconfigured first and/or second intervals are configured based on a rise time and/or a fall time associated with the communication interface and may be calibrated by measuring respective delays associated with clock pulses generated for first and second calibration transitions.

    Abstract translation: 描述了一种方法，装置和计算机程序产品。 该装置通过确定从多线开漏链路接收的信号中的转变来产生用于从多线开漏链路接收数据的接收时钟信号，响应于该转换产生时钟脉冲，延迟时钟脉冲 如果转换处于第一方向，则通过预先配置的第一间隔，并且如果转换处于第二方向，则将时钟延迟预先配置的第二间隔。 基于与通信接口相关联的上升时间和/或下降时间来配置预配置的第一和/或第二间隔，并且可以通过测量与为第一和第二校准转换产生的时钟脉冲相关联的相应延迟来校准预配置的第一和/或第二间隔。

    Run-length detection and correction
    100.
    发明授权
    Run-length detection and correction 有权
    运行长度检测和校正

    公开(公告)号：US09369237B2

    公开(公告)日：2016-06-14

    申请号：US14453287

    申请日：2014-08-06

    Applicant: QUALCOMM Incorporated

    Inventor： George Alan Wiley ,  Chulkyu Lee

    IPC: H04L1/00 ,  H04L12/26 ,  H04L25/02 ,  H04L25/14 ,  H04L25/49

    CPC classification number: H04L1/0056 ,  H04L1/0014 ,  H04L25/0272 ,  H04L25/14 ,  H04L25/49 ,  H04L43/0811

    Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. The apparatus may determine whether a run-length violation will occur or is likely to occur if a first sequence of symbols provided by a mapper of an M-Wire N-Phase encoder is transmitted on a plurality of wires. A second sequence of symbols may be substituted for the first sequence of symbols. The second sequence of symbols may comprise a surplus sequence of symbols that is not used for mapping data in the mapper.

    Abstract translation: 描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个设备之间。 如果由M-Wire N相编码器的映射器提供的第一符号序列在多个导线上传输，则装置可以确定是否会发生游程长度违规或可能发生游程长度违例。 符号的第二序列可以代替第一符号序列。 第二符号序列可以包括不用于映射器中的数据的多余符号序列。

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