公开(公告)号：US20150036437A1

公开(公告)日：2015-02-05

申请号：US13957460

申请日：2013-08-02

Applicant: Qualcomm Incorporated

Inventor： Xia Li ,  Bin Yang ,  Zhongze Wang

IPC: G11C16/10 ,  H01L21/28 ,  H01L29/66

CPC classification number: G11C16/10 ,  G11C16/0433 ,  G11C16/14 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

Abstract: An apparatus includes a storage transistor. The storage transistor includes a floating gate configured to store electrical charge and a control gate. The floating gate is coupled to the control gate via capacitive coupling. The floating gate and the control gate are metal. The apparatus also includes an access transistor coupled to the storage transistor. A gate of the access transistor is coupled to a word line. The storage transistor and the access transistor are serially coupled between a bit line and a source line.

Abstract translation: 一种装置包括存储晶体管。 存储晶体管包括被配置为存储电荷的浮动栅极和控制栅极。 浮动栅极通过电容耦合耦合到控制栅极。 浮动门和控制门是金属的。 该装置还包括耦合到存储晶体管的存取晶体管。 存取晶体管的栅极耦合到字线。 存储晶体管和存取晶体管串联耦合在位线和源极线之间。

公开(公告)号：US20150019147A1

公开(公告)日：2015-01-15

申请号：US13939243

申请日：2013-07-11

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Xiaochun Zhu ,  Seung H. Kang

IPC: G01R31/26

CPC classification number: G01R31/26 ,  G11B5/3166 ,  G11C11/16 ,  G11C29/50 ,  G11C2029/5002 ,  H01L43/12

Abstract: For first and second magnetic tunnel junction (MTJ) elements, a trend in a relationship between an electrical characteristic of the first and second MTJ elements and an area of the first and second MTJ elements may be determined. Damage to a sidewall of the first and second MTJ elements may be estimated from the trend. At least one operating parameter of an MTJ manufacturing apparatus may be modified based on an X or Y intercept a trend line.

Abstract translation: 对于第一和第二磁性隧道结（MTJ）元件，可以确定第一和第二MTJ元件的电特性与第一和第二MTJ元件的面积之间的关系的趋势。 可以从趋势估计对第一和第二MTJ元件的侧壁的损坏。 可以基于X或Y拦截趋势线来修改MTJ制造装置的至少一个操作参数。

公开(公告)号：US08912013B2

公开(公告)日：2014-12-16

申请号：US13720074

申请日：2012-12-19

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Seung H. Kang ,  Xia Li

IPC: H01L21/00 ,  H01L21/02 ,  H01L29/82 ,  G11C27/00 ,  G11C11/00 ,  G11C11/14 ,  G11C11/15 ,  G11C7/00 ,  G11C11/06 ,  H01L43/12 ,  B82Y25/00 ,  B82Y40/00 ,  G01R33/09 ,  H01F10/32 ,  H01F41/30 ,  H01L27/22 ,  H01L43/08 ,  G11C11/16

CPC classification number: H01L43/12 ,  B82Y10/00 ,  B82Y25/00 ,  B82Y40/00 ,  G01R33/098 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01F10/3254 ,  H01F10/3259 ,  H01F10/3268 ,  H01F10/329 ,  H01F10/3295 ,  H01F41/307 ,  H01L27/228 ,  H01L43/08

Abstract: A magnetic tunneling junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, an apparatus is disclosed that includes an MTJ device. The MTJ device includes a free layer and a spin torque enhancing layer. The spin torque enhancing layer includes a nano-oxide layer.

Abstract translation: 公开了一种磁隧道结（MTJ）装置及其制造方法。 在特定实施例中，公开了一种包括MTJ装置的装置。 MTJ装置包括自由层和自旋转矩增强层。 自旋扭矩增强层包括纳米氧化物层。

公开(公告)号：US20140219016A1

公开(公告)日：2014-08-07

申请号：US13759344

申请日：2013-02-05

Applicant: QUALCOMM INCORPORATED

Inventor： Xia Li ,  Bin Yang

IPC: G11C7/12 ,  G11C11/40 ,  G06F17/50

CPC classification number: G11C17/18 ,  G06F17/5045 ,  G11C5/06 ,  G11C5/146 ,  G11C7/12 ,  G11C11/40 ,  G11C11/404 ,  G11C11/5692 ,  G11C16/04 ,  G11C17/16 ,  G11C2211/4016

Abstract: A method includes selectively creating a first breakdown condition and a second breakdown condition at a semiconductor transistor structure. The first breakdown condition is between a source overlap region of the semiconductor transistor structure and a gate of the semiconductor transistor structure. The second breakdown condition is between ad rain overlap region of the semiconductor transistor structure and the gate.

Abstract translation: 一种方法包括在半导体晶体管结构中选择性地产生第一击穿条件和第二击穿条件。 第一击穿条件在半导体晶体管结构的源极重叠区域和半导体晶体管结构的栅极之间。 第二击穿条件是在半导体晶体管结构的覆盖区域和栅极之间。

公开(公告)号：US20140206104A1

公开(公告)日：2014-07-24

申请号：US14219026

申请日：2014-03-19

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Xia Li ,  Wei-Chuan Chen ,  Seung Hyuk Kang

IPC: H01L43/12

CPC classification number: H01L43/12 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1675 ,  H01F10/3254 ,  H01F10/3286 ,  H01F41/325 ,  H01L27/222 ,  H01L41/12 ,  H01L43/08 ,  H01L43/10

Abstract: Partial perpendicular magnetic anisotropy (PPMA) type magnetic random access memory cells are constructed using processes and structural configurations that induce a directed static strain/stress on an MTJ to increase the perpendicular magnetic anisotropy. Consequently, reduced switching current of the MTJ results. The directed static strain/stress on the MTJ is induced in a controlled direction and/or with a controlled magnitude during fabrication. The MTJ is permanently subject to a predetermined directed stress and permanently includes the directed static strain/strain that provides reduced switching current.

Abstract translation: 使用在MTJ上引起定向静态应变/应力以增加垂直磁各向异性的工艺和结构构造来构造部分垂直磁各向异性（PPMA）型磁性随机存取存储器单元。 因此，MTJ的开关电流降低。 在制造过程中，受控方向和/或受控幅度诱发MTJ上的定向静态应变/应力。 MTJ永久地受到预定的定向应力，并且永久地包括提供减小的开关电流的定向静态应变/应变。

公开(公告)号：US20140073064A1

公开(公告)日：2014-03-13

申请号：US14086054

申请日：2013-11-21

Applicant: QUALCOMM Incorporated

Inventor： Seung Hyuk Kang ,  Xia Li ,  Wei-Chuan Chen ,  Kangho Lee ,  Xiaochun Zhu ,  Wah Nam Hsu

IPC: H01L43/12

CPC classification number: H01L43/12 ,  H01L43/08

Abstract: A magnetic tunnel junction (MTJ) with direct contact is manufactured having lower resistances, improved yield, and simpler fabrication. The lower resistances improve both read and write processes in the MTJ. The MTJ layers are deposited on a bottom electrode aligned with the bottom metal. An etch stop layer may be deposited adjacent to the bottom metal to prevent overetch of an insulator surrounding the bottom metal. The bottom electrode is planarized before deposition of the MTJ layers to provide a substantially flat surface. Additionally, an underlayer may be deposited on the bottom electrode before the MTJ layers to promote desired characteristics of the MTJ.

Abstract translation: 具有直接接触的磁性隧道结（MTJ）被制造成具有较低的电阻，提高的产量和更简单的制造。 较低的电阻提高了MTJ中的读取和写入过程。 MTJ层沉积在与底部金属对准的底部电极上。 蚀刻停止层可以沉积在底部金属附近，以防止围绕底部金属的绝缘体的过蚀刻。 在沉积MTJ层之前将底部电极平坦化以提供基本平坦的表面。 另外，可以在MTJ层之前的底部电极上沉​​积底层以促进MTJ的期望特性。

公开(公告)号：US20140035075A1

公开(公告)日：2014-02-06

申请号：US14048704

申请日：2013-10-08

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Seung Hyuk Kang ,  Xia Li ,  Kangho Lee

IPC: H01L43/02 ,  H01L43/12

CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: A magnetic tunnel junction device includes a Synthetic Anti-Ferromagnetic (SAF) layer, a first free layer, and second free layer. The magnetic tunnel junction device further includes a spacer layer between the first and second free layers. The first free layer is magneto-statically coupled to the second free layer. A thickness of the spacer layer is at least 4 Angstroms.

Abstract translation: 磁性隧道结装置包括合成反铁磁（SAF）层，第一自由层和第二自由层。 磁性隧道结装置还包括在第一和第二自由层之间的间隔层。 第一自由层被磁静态耦合到第二自由层。 间隔层的厚度至少为4埃。

公开(公告)号：US08642990B2

公开(公告)日：2014-02-04

申请号：US13762424

申请日：2013-02-08

Applicant: Qualcomm Incorporated

Inventor： Xia Li

IPC: H01L29/06

CPC classification number: H01L45/06 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/008 ,  G11C2213/52 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/122 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1675

Abstract: A method of forming a phase-change random access memory (PRAM) cell, and a structure of a phase-change random access memory (PRAM) cell are disclosed. The PRAM cell includes a bottom electrode, a heater resistor coupled to the bottom electrode, a phase change material (PCM) formed over and coupled to the heater resistor, and a top electrode coupled to the phase change material. The phase change material contacts a portion of a vertical surface of the heater resistor and a portion of a horizontal surface of the heater resistor to form an active region between the heater resistor and the phase change material.

Abstract translation: 公开了形成相变随机存取存储器（PRAM）单元的方法以及相变随机存取存储器（PRAM）单元的结构。 PRAM单元包括底电极，耦合到底电极的加热电阻器，形成在加热电阻器上并耦合到加热电阻器的相变材料（PCM）以及耦合到相变材料的顶电极。 相变材料接触加热器电阻器的垂直表面的一部分和加热电阻器的水平表面的一部分，以在加热电阻器和相变材料之间形成有源区域。

公开(公告)号：US20140021570A1

公开(公告)日：2014-01-23

申请号：US14036354

申请日：2013-09-25

Applicant: QUALCOMM INCORPORATED

Inventor： Wei-Chuan Chen ,  Xia Li ,  Seung Hyuk Kang

IPC: H01L43/12 ,  H01L43/02

CPC classification number: G11C11/16 ,  G11C11/161 ,  H01L23/552 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and apparatus for shielding a shielding a non-volatile memory, such as shielding a magnetic tunnel junction (MTJ) device from a magnetic flux are provided. In an example, a shielding layer is formed adjacent to an electrode of an MTJ device, such that the shielding layer substantially surrounds a surface of the electrode, and a metal line is coupled to the shielding layer. The metal line can be coupled to the shielding layer by a via.

Abstract translation: 提供了用于屏蔽屏蔽非易失性存储器的方法和装置，例如屏蔽磁性隧道结（MTJ）装置与磁通量。 在一个示例中，屏蔽层邻近MTJ器件的电极形成，使得屏蔽层基本上围绕电极的表面，并且金属线耦合到屏蔽层。 金属线可以通过通孔耦合到屏蔽层。

公开(公告)号：US20130244345A1

公开(公告)日：2013-09-19

申请号：US13887492

申请日：2013-05-06

Applicant: QUALCOMM INCORPORATED

Inventor： Xia Li ,  Seung H. Kang

IPC: H01L43/12

CPC classification number: H01L43/12 ,  B82Y25/00 ,  B82Y40/00 ,  G11C11/161 ,  H01F10/3254 ,  H01F41/307 ,  H01L27/222 ,  H01L43/08

Abstract: An electronic device manufacturing process includes depositing a bottom electrode layer. Then an electronic device is fabricated on the bottom electrode layer. Patterning of the bottom electrode layer is performed after fabricating the electronic device and in a separate process from patterning a top electrode. A first dielectric layer is then deposited on the electronic device and the bottom electrode layer followed by a top electrode layer. The top electrode is then patterned in a separate process from the bottom electrode. Separately patterning the top and bottom electrodes improves yields by reducing voids in the dielectric material between electronic devices. One electronic device the manufacturing process is well-suited for is magnetic tunnel junctions (MTJs).

Abstract translation: 电子器件制造工艺包括沉积底部电极层。 然后在底部电极层上制造电子器件。 底部电极层的图案化是在制造电子器件之后并且在单独的工艺中对图案化顶部电极进行的。 然后在电子器件上沉积第一电介质层，然后在底部电极层上沉积第一电介质层，然后是顶部电极层。 然后在与底部电极分离的工艺中对顶部电极进行图案化。 单独图案化顶部和底部电极通过减少电子器件之间的电介质材料中的空隙来提高产率。 一种电子设备，其制造工艺非常适用于磁隧道结（MTJ）。