公开(公告)号：US20110086475A1

公开(公告)日：2011-04-14

申请号：US12968656

申请日：2010-12-15

申请人： Shunpei YAMAZAKI ,  Yasuyuki ARAI ,  Ikuko KAWAMATA

发明人： Shunpei YAMAZAKI ,  Yasuyuki ARAI ,  Ikuko KAWAMATA

IPC分类号： H01L21/336

CPC分类号： H01L27/11546 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/1255 ,  H01L29/66825 ,  H01L29/7881

摘要： In order to form a plurality of semiconductor elements over an insulating surface, in one continuous semiconductor layer, an element region serving as a semiconductor element and an element isolation region having a function to electrically isolate element regions from each other by repetition of PN junctions. The element isolation region is formed by selective addition of an impurity element of at least one or more kinds of oxygen, nitrogen, and carbon and an impurity element that imparts an opposite conductivity type to that of the adjacent element region in order to electrically isolate elements from each other in one continuous semiconductor layer.

摘要翻译： 为了在绝缘表面上形成多个半导体元件，在一个连续半导体层中，用作半导体元件的元件区域和具有通过重复PN结将元件区域彼此电隔离的功能的元件隔离区域。 通过选择性地添加至少一种或多种氧，氮和碳的杂质元素和赋予与相邻元件区相反的导电类型的杂质元素来形成元件隔离区域，以便电隔离元件 在一个连续的半导体层中彼此相交。

公开(公告)号：US20110084264A1

公开(公告)日：2011-04-14

申请号：US12897160

申请日：2010-10-04

申请人： Shunpei YAMAZAKI ,  Masayuki SAKAKURA ,  Akiharu MIYANAGA ,  Masahiro TAKAHASHI ,  Takuya HIROHASHI ,  Takashi SHIMAZU

发明人： Shunpei YAMAZAKI ,  Masayuki SAKAKURA ,  Akiharu MIYANAGA ,  Masahiro TAKAHASHI ,  Takuya HIROHASHI ,  Takashi SHIMAZU

IPC分类号： H01L29/12

CPC分类号： H01L29/7869 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78693 ,  H01L29/78696

摘要： An object is to provide an oxide semiconductor layer having a novel structure which is preferably used for a semiconductor device. Alternatively, another object is to provide a semiconductor device using an oxide semiconductor layer having the novel structure. An oxide semiconductor layer includes an amorphous region which is mainly amorphous and a crystal region containing crystal grains of In2Ga2ZnO7 in a vicinity of a surface, in which the crystal grains are oriented so that the c-axis is almost vertical with respect to the surface. Alternatively, a semiconductor device uses such an oxide semiconductor layer.

摘要翻译： 目的在于提供一种具有新的结构的氧化物半导体层，其优选用于半导体器件。 或者，另一个目的是提供一种使用具有新颖结构的氧化物半导体层的半导体器件。 氧化物半导体层包括主要为非晶质的非晶区域和在表面附近含有In2Ga2ZnO7晶体的晶体区域，其中晶粒取向为使得c轴相对于表面几乎垂直。 或者，半导体器件使用这种氧化物半导体层。

公开(公告)号：US20110075038A1

公开(公告)日：2011-03-31

申请号：US12964838

申请日：2010-12-10

申请人： Shunpei YAMAZAKI ,  Hajime KIMURA ,  Mai AKIBA ,  Aya ANZAI ,  Yu YAMAZAKI

发明人： Shunpei YAMAZAKI ,  Hajime KIMURA ,  Mai AKIBA ,  Aya ANZAI ,  Yu YAMAZAKI

IPC分类号： H04N5/30

CPC分类号： G09G3/006 ,  G09G3/2022 ,  G09G3/3233 ,  G09G3/3266 ,  G09G3/3291 ,  G09G2300/0809 ,  G09G2300/0842 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2310/061 ,  G09G2320/0233 ,  G09G2320/0285 ,  G09G2320/029 ,  G09G2320/0295 ,  G09G2320/043 ,  G09G2320/048 ,  G09G2320/0693

摘要： To provide a light emitting device without nonuniformity of luminance, a correcting circuit for correcting a video signal supplied to each pixel to a light emitting device. The correcting circuit is stored with data of a dispersion of a characteristic of a driving TFT among pixels and data of a change over time of luminance of a light emitting element. Further, by correcting a video signal inputted to the light emitting device in conformity with a characteristic of the driving TFT of each pixel and a degree of a deterioration of the light emitting element based on the over-described two data, nonuniformity of luminance caused by a deterioration of an electroluminescent layer and nonuniformity of luminance caused by dispersion of a characteristic of the driving TFT are restrained.

摘要翻译： 为了提供没有不均匀亮度的发光器件，用于将提供给每个像素的视频信号校正到发光器件的校正电路。 校正电路与像素中的驱动TFT的特性的色散的数据和发光元件的亮度随时间的变化的数据一起存储。 此外，通过根据上述两个数据，校正根据每个像素的驱动TFT的特性和发光元件的劣化程度输入到发光器件的视频信号，由 抑制了电致发光层的劣化以及由驱动TFT的特性的分散引起的亮度的不均匀性。

公开(公告)号：US20110073934A1

公开(公告)日：2011-03-31

申请号：US12963847

申请日：2010-12-09

申请人： Tamae TAKANO ,  Tetsuya KAKEHATA ,  Shunpei YAMAZAKI

发明人： Tamae TAKANO ,  Tetsuya KAKEHATA ,  Shunpei YAMAZAKI

IPC分类号： H01L29/792

CPC分类号： H01L27/1157 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L27/1214 ,  H01L27/1251 ,  H01L27/13 ,  H01L29/4234 ,  H01L29/792 ,  H01L29/7923

摘要： The invention provides a semiconductor device and its manufacturing method in which a memory transistor and a plurality of thin film transistors that have gate insulating films with different thicknesses are fabricated over a substrate. The invention is characterized by the structural difference between the memory transistor and the plurality of thin film transistors. Specifically, the memory transistor and some of the plurality of thin film transistors are provided to have a bottom gate structure while the other thin film transistors are provided to have a top gate structure, which enables the reduction of characteristic defects of the transistor and simplification of its manufacturing process.

公开(公告)号：US20110068438A1

公开(公告)日：2011-03-24

申请号：US12952925

申请日：2010-11-23

申请人： Shunpei YAMAZAKI ,  Yasuyuki ARAI

发明人： Shunpei YAMAZAKI ,  Yasuyuki ARAI

IPC分类号： H01L29/06

CPC分类号： G06K19/07749 ,  G06K19/07728 ,  G06K19/0775 ,  H01L23/49855 ,  H01L23/66 ,  H01L24/48 ,  H01L24/73 ,  H01L2223/6677 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/19041 ,  H01Q1/2216 ,  H01Q23/00 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In inlets used for ID tags and the like, a defective connection between an integrated circuit part and an antenna is suppressed by improvement of tolerance for a bending or a pressing pressure. The integrated circuit part includes a semiconductor chip and a multilayer substrate having a concave portion. The semiconductor chip is mounted on the bottom of the concave portion. The multilayer substrate includes a connection electrode at the top surface and a connection electrode connected to the semiconductor chip on the bottom of the concave portion. The connection electrode on the bottom of the concave portion is connected to the connection electrode at the top surface by a penetration electrode inside a multilayer substrate. By such a configuration, the semiconductor chip is connected to the antenna.

摘要翻译： 在用于ID标签等的入口中，通过提高弯曲或按压压力的公差来抑制集成电路部件和天线之间的有缺陷的连接。 集成电路部分包括半导体芯片和具有凹部的多层基板。 半导体芯片安装在凹部的底部。 多层基板包括在顶表面处的连接电极和连接到凹部底部的半导体芯片的连接电极。 凹部的底部的连接电极通过多层基板内的贯通电极在顶面与连接电极连接。 通过这样的结构，将半导体芯片连接到天线。

公开(公告)号：US20110062461A1

公开(公告)日：2011-03-17

申请号：US12949165

申请日：2010-11-18

申请人： Shunpei YAMAZAKI ,  Yasuyuki ARAI

发明人： Shunpei YAMAZAKI ,  Yasuyuki ARAI

IPC分类号： H01L33/08

CPC分类号： H01L51/5237 ,  H01L27/3244 ,  H01L51/524 ,  H01L51/5259 ,  H01L51/5275 ,  H01L51/5281 ,  H01L2251/5315 ,  H05B33/04

摘要： An organic EL display device of active matrix type wherein insulated-gate field effect transistors formed on a single-crystal semiconductor substrate are overlaid with an organic EL layer; characterized in that the single-crystal semiconductor substrate (413 in FIG. 4) is held in a vacant space (414) which is defined by a bed plate (401) and a cover plate (405) formed of an insulating material, and a packing material (404) for bonding the bed and cover plates; and that the vacant space (414) is filled with an inert gas and a drying agent, whereby the organic EL layer is prevented from oxidizing.

摘要翻译： 其中有源矩阵型的有机EL显示器件，其中形成在单晶半导体衬底上的绝缘栅场效应晶体管与有机EL层重叠; 其特征在于，单晶半导体衬底（图4中的413）保持在由隔板（401）和由绝缘材料形成的盖板（405）限定的空白空间（414）中，并且 包装材料（404），用于粘合床和盖板; 并且空置空间（414）填充有惰性气体和干燥剂，由此防止有机EL层氧化。

公开(公告)号：US20110057186A1

公开(公告)日：2011-03-10

申请号：US12869278

申请日：2010-08-26

申请人： Shunpei YAMAZAKI ,  Toshinari SASAKI ,  Junichiro SAKATA ,  Masashi TSUBUKU

发明人： Shunpei YAMAZAKI ,  Toshinari SASAKI ,  Junichiro SAKATA ,  Masashi TSUBUKU

IPC分类号： H01L29/786

CPC分类号： H01L27/1225 ,  H01L27/1214 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/3248 ,  H01L27/3262 ,  H01L27/3265 ,  H01L29/24 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78693

摘要： It is an object to manufacture a highly reliable display device using a thin film transistor having favorable electric characteristics and high reliability as a switching element. In a bottom gate thin film transistor including an amorphous oxide semiconductor, an oxide conductive layer having a crystal region is formed between an oxide semiconductor layer which has been dehydrated or dehydrogenated by heat treatment and each of a source electrode layer and a drain electrode layer which are formed using a metal material. Accordingly, contact resistance between the oxide semiconductor layer and each of the source electrode layer and the drain electrode layer can be reduced; thus, a thin film transistor having favorable electric characteristics and a highly reliable display device using the thin film transistor can be provided.

摘要翻译： 本发明的目的是制造使用具有良好的电特性和高可靠性的薄膜晶体管作为开关元件的高度可靠的显示装置。 在包括非晶氧化物半导体的底栅薄膜晶体管中，在已经通过热处理脱水或脱氢的氧化物半导体层与源电极层和漏电极层中的每一个之间形成具有晶体区的氧化物导电层， 使用金属材料形成。 因此，可以减小氧化物半导体层与源极电极层和漏极电极层中的每一个之间的接触电阻; 因此，可以提供具有良好电特性的薄膜晶体管和使用该薄膜晶体管的高度可靠的显示装置。

公开(公告)号：US20110031501A1

公开(公告)日：2011-02-10

申请号：US12904536

申请日：2010-10-14

申请人： Hideomi SUZAWA ,  Shunpei YAMAZAKI

发明人： Hideomi SUZAWA ,  Shunpei YAMAZAKI

IPC分类号： H01L33/16

CPC分类号： H01L51/56 ,  H01L27/3246 ,  H01L27/3248 ,  H01L27/3258 ,  H01L27/3262 ,  H01L51/5206 ,  H01L51/5234 ,  H01L51/5246 ,  H01L51/5259 ,  H01L2251/5315 ,  H01L2251/5323

摘要： According to one feature of the present invention, a display device is manufactured according to the steps of forming a semiconductor layer; forming a gate insulating layer over the semiconductor layer; forming a gate electrode layer over the gate insulating layer; forming source and drain electrode layers in contact with the semiconductor layer; forming a first electrode layer electrically connected to the source or drain electrode layer; forming an inorganic insulating layer over part of the first electrode layer, the gate electrode layer, the source electrode layer, and the drain electrode layer; subjecting the inorganic insulating layer and the first electrode layer to plasma treatment; forming an electroluminescent layer over the inorganic insulating layer and the first electrode layer which are subjected to plasma treatment; and forming a second electrode layer over the electroluminescent layer.

摘要翻译： 根据本发明的一个特征，根据形成半导体层的步骤制造显示装置; 在所述半导体层上形成栅极绝缘层; 在所述栅绝缘层上形成栅电极层; 形成与半导体层接触的源极和漏极电极层; 形成电连接到所述源极或漏极电极层的第一电极层; 在所述第一电极层，所述栅极电极层，所述源极电极层和所述漏极电极层的一部分上形成无机绝缘层; 对无机绝缘层和第一电极层进行等离子体处理; 在经过等离子体处理的无机绝缘层和第一电极层上形成电致发光层; 以及在所述电致发光层上形成第二电极层。

公开(公告)号：US20110027968A1

公开(公告)日：2011-02-03

申请号：US12899993

申请日：2010-10-07

申请人： Shunpei YAMAZAKI ,  Hideto OHNUMA ,  Tetsuya KAKEHATA

发明人： Shunpei YAMAZAKI ,  Hideto OHNUMA ,  Tetsuya KAKEHATA

IPC分类号： H01L21/762

CPC分类号： H01L27/1266 ,  H01L21/31662 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/1214 ,  H01L27/1229 ,  H01L29/66772 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2224/80001

摘要： A semiconductor device including a plurality of field-effect transistors which are stacked with a planarization layer interposed therebetween over a substrate having an insulating surface, in which semiconductor layers in the plurality of field-effect transistors are separated from semiconductor substrates, and the semiconductor layers are bonded to an insulating layer formed over the substrate having an insulating surface or an insulating layer formed over the planarization layer.

摘要翻译： 一种半导体器件，包括多个场效应晶体管，所述多个场效应晶体管在其间具有绝缘表面的衬底上层叠有平坦化层，所述多个场效应晶体管中的半导体层与半导体衬底分离，并且所述半导体层 被结合到形成在具有形成在平坦化层上的绝缘表面或绝缘层的衬底上的绝缘层。

公开(公告)号：US20110006301A1

公开(公告)日：2011-01-13

申请号：US12832333

申请日：2010-07-08

申请人： Shunpei YAMAZAKI ,  Hiroki OHARA ,  Junichiro SAKATA ,  Toshinari SASAKI ,  Miyuki HOSOBA

发明人： Shunpei YAMAZAKI ,  Hiroki OHARA ,  Junichiro SAKATA ,  Toshinari SASAKI ,  Miyuki HOSOBA

IPC分类号： H01L29/786 ,  H01L21/34

CPC分类号： H01L27/127 ,  H01L21/477 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1274 ,  H01L27/1296 ,  H01L29/04 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78693

摘要： An object is to manufacture and provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which a semiconductor layer including a channel formation region serves as an oxide semiconductor film, heat treatment for reducing impurities such as moisture (heat treatment for dehydration or dehydrogenation) is performed after an oxide insulating film serving as a protective film is formed in contact with an oxide semiconductor layer. Then, the impurities such as moisture, which exist not only in a source electrode layer, in a drain electrode layer, in a gate insulating layer, and in the oxide semiconductor layer but also at interfaces between the oxide semiconductor film and upper and lower films which are in contact with the oxide semiconductor layer, are reduced.

摘要翻译： 目的是制造和提供包括具有稳定电特性的薄膜晶体管的高度可靠的半导体器件。 在包括薄膜晶体管的半导体器件的制造方法中，其中包括沟道形成区域的半导体层用作氧化物半导体膜，用于减少诸如水分的杂质（脱水或脱氢热处理）的热处理在 形成与氧化物半导体层接触的用作保护膜的氧化物绝缘膜。 然后，在漏极电极层，栅极绝缘层和氧化物半导体层中以及在氧化物半导体膜和上下膜之间的界面处不仅在源电极层中存在的诸如水分的杂质 它们与氧化物半导体层接触。