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公开(公告)号：US10522226B2
公开(公告)日：2019-12-31
申请号：US16042972
申请日：2018-07-23
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Thuan Vu , Stanley Hong , Anh Ly , Vipin Tiwari , Nhan Do
IPC: G11C16/04 , G06N3/08 , H01L27/11521 , H01L29/788
Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Optionally, compensation measures can be utilized that compensate for changes in voltage or current as the number of cells being programmed changes.
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公开(公告)号：US10297327B2
公开(公告)日：2019-05-21
申请号：US15952155
申请日：2018-04-12
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen
IPC: G11C16/26 , G11C16/14 , G11C16/08 , G11C7/06 , G11C8/08 , G11C16/10 , G11C16/28 , H01L27/112 , H01L27/11582 , H01L49/02
Abstract: The present invention relates to a flash memory system comprising one or more sense amplifiers for reading data stored in flash memory cells. The sense amplifiers utilize fully depleted silicon-on-insulator transistors to minimize leakage. The fully depleted silicon-on-insulator transistors comprise one or more fully depleted silicon-on-insulator NMOS transistors and/or one or more fully depleted silicon-on-insulator PMOS transistors.
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93.发明授权公开(公告)号：US10269432B2
公开(公告)日：2019-04-23
申请号：US15479235
申请日：2017-04-04
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Anh Ly , Thuan Vu , Vipin Tiwari , Nhan Do
IPC: G11C16/06 , G11C16/08 , G11C16/14 , G11C16/24 , G11C16/34 , G11C16/26 , G11C16/04 , G11C16/10 , G11C16/28 , G11C16/32
Abstract: In one embodiment of the present invention, one row is selected and two columns are selected for a read or programming operation, such that twice as many flash memory cells can be read from or programmed in a single operation compared to the prior art. In another embodiment of the present invention, two rows in different sectors are selected and one column is selected for a read operation, such that twice as many flash memory cells can be read in a single operation compared to the prior art.
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公开(公告)号：US20180047454A1
公开(公告)日：2018-02-15
申请号：US15792590
申请日：2017-10-24
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen , Vipin Tiwari
CPC classification number: G11C16/28 , G11C7/062 , G11C7/067 , G11C7/12 , G11C16/00 , G11C16/06 , G11C16/24 , G11C16/26 , G11C2207/063 , H01L27/11519
Abstract: Improved flash memory sensing circuits are disclosed. In one embodiment, a sensing circuit comprises a memory data read block, a memory reference block, a differential amplifier, and a precharge circuit. The precharge circuit compensates for parasitic capacitance between a bit line coupled to a selected memory cell and adjacent bit lines.
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公开(公告)号：US20170358360A1
公开(公告)日：2017-12-14
申请号：US15687191
申请日：2017-08-25
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen
Abstract: An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed.
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Patent Agency Ranking
公开(公告)号：US20170345509A1
公开(公告)日：2017-11-30
申请号：US15163548
申请日：2016-05-24
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Anh Ly , Thuan Vu
CPC classification number: G11C16/28 , G11C7/065 , G11C16/0433 , G11C16/14 , G11C16/24
Abstract: The present invention relates to an improved sensing amplifier and related method for use in read operations in flash memory devices. In one embodiment, the sensing amplifier includes a built-in voltage offset. In another embodiment, a voltage offset is induced in the sensing amplifier through the use of capacitors. In another embodiment, the sensing amplifier utilizes sloped timing for the reference signal to increase the margin by which a “0” or “1” are detected from the current drawn by the selected cell compared to the reference cell. In an another embodiment, a sensing amplifier is used without any voltage offset.
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公开(公告)号：US20170269662A1
公开(公告)日：2017-09-21
申请号：US15610612
申请日：2017-05-31
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Thuan Vu , Anh Ly , Hung Quoc Nguyen
CPC classification number: G06F1/266 , G06F1/28 , G11C5/14 , G11C5/143 , G11C5/147 , G11C5/148 , G11C7/20 , G11C11/4074 , G11C16/30 , H03K19/018521
Abstract: A system and method for improved power sequencing within an embedded flash memory device is disclosed.
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公开(公告)号：US09672930B2
公开(公告)日：2017-06-06
申请号：US14726124
申请日：2015-05-29
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen , Viet Tan Nguyen
IPC: G11C7/00 , G11C16/30 , G11C16/08 , G11C16/10 , G11C16/28 , G11C8/10 , G11C5/14 , G11C16/32 , G11C29/14
CPC classification number: G11C16/30 , G11C5/14 , G11C8/10 , G11C16/08 , G11C16/10 , G11C16/28 , G11C16/32 , G11C29/14 , G11C2207/2227
Abstract: The present invention relates to a circuit and method for low power operation in a flash memory system. In disclosed embodiments of a selection-decoding circuit path, pull-up and pull-down circuits are used to save values at certain output nodes during a power save or shut down modes, which allows the main power source to be shut down while still maintaining the values.
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公开(公告)号：US20160240260A1
公开(公告)日：2016-08-18
申请号：US15135346
申请日：2016-04-21
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen
CPC classification number: G11C16/30 , G11C5/14 , G11C5/145 , G11C5/147 , G11C8/08 , G11C16/0408 , G11C16/0425 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/26 , G11C2216/04 , H01L27/11521
Abstract: A non-volatile memory device comprises a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is located in the semiconductor substrate and arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. During the operations of program, read, or erase, a negative voltage can be applied to the word lines and/or coupling gates of the selected or unselected memory cells.
Abstract translation: 非易失性存储器件包括第一导电类型的半导体衬底。 非易失性存储单元的阵列位于半导体衬底中并且被布置成多个行和列。 每个存储单元包括第二导电类型的半导体衬底的表面上的第一区域和第二导电类型的半导体衬底的表面上的第二区域。 沟道区域在第一区域和第二区域之间。 字线覆盖在沟道区域的第一部分上，并且与第一区域绝缘，并且与第一区域相邻并且与第一区域几乎没有或没有重叠。 浮动栅极覆盖沟道区域的第二部分，与第一部分相邻，并与第二部分绝缘并与第二区域相邻。 耦合栅极覆盖浮栅。 位线连接到第一区域。 在程序，读取或擦除的操作期间，负电压可以被施加到所选择的或未选择的存储单元的字线和/或耦合门。
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公开(公告)号：US09417675B2
公开(公告)日：2016-08-16
申请号：US14290779
申请日：2014-05-29
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Thuan Vu , Anh Ly , Hung Quoc Nguyen
CPC classification number: G06F1/266 , G06F1/28 , G11C5/14 , G11C5/143 , G11C5/147 , G11C5/148 , G11C7/20 , G11C11/4074 , G11C16/30 , H03K19/018521
Abstract: A system and method for improved power sequencing within an embedded flash memory device is disclosed.
Abstract translation: 公开了一种用于改进嵌入式闪存设备内的电源排序的系统和方法。
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