公开(公告)号：US20050035371A1

公开(公告)日：2005-02-17

申请号：US10658780

申请日：2003-09-10

申请人： Tatsuhiko Fujihira

发明人： Tatsuhiko Fujihira

IPC分类号： H01L21/331 ,  H01L21/336 ,  H01L29/06 ,  H01L29/739 ,  H01L29/78 ,  H01L29/861 ,  H01L29/872 ,  H01L31/109

CPC分类号： H01L29/7802 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/872

摘要： A semiconductor device having an alternating conductivity type layer improves the tradeoff between the on-resistance and the breakdown voltage and facilitates increasing the current capacity by reducing the on-resistance while maintaining a high breakdown voltage. The semiconductor device includes a semiconductive substrate region, through which a current flows in the ON-state of the device and that is depleted in the OFF-state. The semiconductive substrate region includes a plurality of vertical alignments of n-type buried regions 32 and a plurality of vertical alignments of p-type buried regions. The vertically aligned n-type buried regions and the vertically aligned p-type buried regions are alternately arranged horizontally. The n-type buried regions and p-type buried regions are formed by diffusing respective impurities into highly resistive n-type layers 32a laminated one by one epitaxially.

摘要翻译： 具有交变导电型层的半导体器件改善了导通电阻和击穿电压之间的折衷，并且通过在保持高击穿电压的同时降低导通电阻来增加电流容量。 半导体器件包括半导体衬底区域，电流在器件的导通状态中流过该半导体衬底区域，并且在OFF状态下耗尽。 半导体衬底区域包括n型埋入区32的多个垂直对准和p型埋入区的多个垂直对准。 垂直取向的n型掩埋区域和垂直排列的p型掩埋区域水平地交替排列。 通过将各种杂质扩散到外延层叠的高电阻性n型层32a中，形成n型掩埋区域和p型掩埋区域。

公开(公告)号：US06759301B2

公开(公告)日：2004-07-06

申请号：US10461094

申请日：2003-06-13

申请人： Manabu Takei ,  Tatsuhiko Fujihira

发明人： Manabu Takei ,  Tatsuhiko Fujihira

IPC分类号： H01L21336

CPC分类号： H01L29/66712 ,  H01L21/263 ,  H01L29/32 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/861

摘要： A semiconductor device is provided which can be manufactured even by using an inexpensive FZ wafer in a wafer process and still has a sharp inclination of a high impurity concentration in a high impurity concentration layer at the outermost portion of the reverse side and at the boundary between the high impurity concentration and a low impurity concentration drift layer, thus achieving both low cost and a high performance. A method for manufacturing a semiconductor device is also provided which can form a high impurity concentration buffer layer and a high impurity concentration layer at the outermost portion of the reverse side without any significant trouble, even after the formation of an active region and an electrode thereof at the right side, to thereby achieve both low cost and high performance.

摘要翻译： 提供了一种半导体器件，其可以通过在晶片工艺中使用便宜的FZ晶片来制造，并且在反面的最外部分的高杂质浓度层和在反面的最外部处以及在相反侧的边界处仍然具有高杂质浓度的尖锐倾斜 高杂质浓度和低杂质浓度漂移层，从而实现低成本和高性能。 还提供了一种用于制造半导体器件的方法，即使在形成有源区和其电极之后，也可以在反面的最外部形成高杂质浓度缓冲层和高杂质浓度层，而没有任何明显的麻烦 在右侧，从而实现低成本和高性能。

公开(公告)号：US06683347B1

公开(公告)日：2004-01-27

申请号：US09348915

申请日：1999-07-07

申请人： Tatsuhiko Fujihira

发明人： Tatsuhiko Fujihira

IPC分类号： H01L2976

CPC分类号： H01L29/7802 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/872

摘要： A semiconductor device having an alternating conductivity type layer improves the tradeoff between the on-resistance and the breakdown voltage and facilitates increasing the current capacity by reducing the on- resistance while maintaining a high breakdown voltage. The semiconductor device includes a semiconductive substrate region, through which a current flows in the ON-state of the device and that is depleted in the OFF-state. The semiconductive substrate region includes a plurality of vertical alignments of n-type buried regions 32 and a plurality of vertical alignments of p-type buried regions. The vertically aligned n-type buried regions and the vertically aligned p-type buried regions are alternately arranged horizontally. The n-type buried regions and p-type buried regions are formed by diffusing respective impurities into highly resistive n-type layers 32a laminated one by one epitaxially.

摘要翻译： 具有交替导电型层的半导体器件改善了导通电阻和击穿电压之间的折衷，并且通过在保持高击穿电压的同时降低导通电阻来增加电流容量。 半导体器件包括半导体衬底区域，电流在器件的导通状态中流过该半导体衬底区域，并且在OFF状态下耗尽。 半导体衬底区域包括n型埋入区32的多个垂直对准和p型埋入区的多个垂直对准。 垂直取向的n型掩埋区域和垂直排列的p型掩埋区域水平地交替排列。 通过将各种杂质扩散到外延层叠的高电阻性n型层32a中，形成n型掩埋区域和p型掩埋区域。

公开(公告)号：US06627948B1

公开(公告)日：2003-09-30

申请号：US09583016

申请日：2000-05-30

申请人： Tatsuhiko Fujihira

发明人： Tatsuhiko Fujihira

IPC分类号： H01L2976

CPC分类号： H01L29/7816 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0843 ,  H01L29/1012 ,  H01L29/1095 ,  H01L29/7397 ,  H01L29/7801 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7835 ,  H01L29/78624 ,  H01L29/78696 ,  H01L29/808 ,  H01L29/812 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has a drift region in which a drift current flows if it is in the ON mode and which is depleted if it is in the OFF mode. The drift region is formed as a structure having a plurality of first conductive type divided drift regions and a plurality of second conductive type compartment regions in which each of the compartment regions is positioned among the adjacent drift regions in parallel to make p-n junctions, respectively.

摘要翻译： 如果半导体器件处于导通模式，则漂移电流流过漂移区域，如果它处于关闭模式，则其被耗尽。 漂移区域形成为具有多个第一导电型划分漂移区域和多个第二导电型隔室区域的结构，其中每个隔间区域分别位于相邻漂移区域中以形成p-n结。

公开(公告)号：US06551909B1

公开(公告)日：2003-04-22

申请号：US09629711

申请日：2000-07-31

申请人： Tatsuhiko Fujihira

发明人： Tatsuhiko Fujihira

IPC分类号： H01L2104

CPC分类号： H01L29/7802 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/872

摘要： A semiconductor device having an alternating conductivity type layer improves the tradeoff between the on-resistance and the breakdown voltage and facilitates increasing the current capacity by reducing the on-resistance while maintaining a high breakdown voltage. The semiconductor device includes a semiconductive substrate region, through which a current flows in the ON-state of the device and that is depleted in the OFF-state. The semiconductive substrate region includes a plurality of vertical alignments of n-type buried regions 32 and a plurality of vertical alignments of p-type buried regions. The vertically aligned n-type buried regions and the vertically aligned p-type buried regions are alternately arranged horizontally. The n-type buried regions and p-type buried regions are formed by diffusing respective impurities into highly resistive n-type layers 32a laminated one by one epitaxially.

摘要翻译： 具有交变导电型层的半导体器件改善了导通电阻和击穿电压之间的折衷，并且通过在保持高击穿电压的同时降低导通电阻来增加电流容量。 半导体器件包括半导体衬底区域，电流在器件的导通状态中流过该半导体衬底区域，并且在OFF状态下耗尽。 半导体衬底区域包括n型埋入区32的多个垂直对准和p型埋入区的多个垂直对准。 垂直取向的n型掩埋区域和垂直排列的p型掩埋区域水平地交替排列。 通过将各种杂质扩散到外延层叠的高电阻性n型层32a中，形成n型掩埋区域和p型掩埋区域。

公开(公告)号：US6097063A

公开(公告)日：2000-08-01

申请号：US786473

申请日：1997-01-21

申请人： Tatsuhiko Fujihira

发明人： Tatsuhiko Fujihira

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78 ,  H01L29/786 ,  H01L29/808 ,  H01L29/812 ,  H01L29/94 ,  H01L29/749

CPC分类号： H01L29/7816 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0843 ,  H01L29/1012 ,  H01L29/1095 ,  H01L29/7397 ,  H01L29/7801 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7835 ,  H01L29/78624 ,  H01L29/78696 ,  H01L29/808 ,  H01L29/812 ,  H01L2924/0002

摘要： A semiconductor device has a drift region in which a drift current flows if it is in the ON mode and which is depleted if it is in the OFF mode. The drift region is formed as a structure having a plurality of first conductive type divided drift regions and a plurality of second conductive type compartment regions in which each of the compartment regions is positioned among the adjacent drift regions in parallel to make p-n junctions, respectively.

摘要翻译： 如果半导体器件处于导通模式，则漂移电流流过漂移区域，如果它处于关闭模式，则其被耗尽。 漂移区域形成为具有多个第一导电型划分漂移区域和多个第二导电型隔室区域的结构，其中每个隔间区域分别位于相邻漂移区域中以形成p-n结。

公开(公告)号：US5973359A

公开(公告)日：1999-10-26

申请号：US190929

申请日：1998-11-12

申请人： Takashi Kobayashi ,  Tatsuhiko Fujihira ,  Shigeyuki Takeuchi ,  Yoshiki Kondo ,  Shoichi Furuhata

发明人： Takashi Kobayashi ,  Tatsuhiko Fujihira ,  Shigeyuki Takeuchi ,  Yoshiki Kondo ,  Shoichi Furuhata

IPC分类号： H01L29/739 ,  H01L21/76 ,  H01L27/02 ,  H01L27/04 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/7395 ,  H01L27/0251 ,  H01L27/0255 ,  H01L29/1095 ,  H01L29/7808 ,  H01L29/7811

摘要： A MOS type semiconductor device is provided which includes a series Zener diode array for overvoltage protection, which is provided between source regions and an electrode having substantially the same potential as a drain electrode, and a field insulating film on which the series Zener diode array is provided. The thickness T (.mu.m) of the field insulating film is determined as a function of the clamp voltage V.sub.CE (V) of the series Zener diode array, such that the thickness T is held in the range as represented by: T.gtoreq.2.0.times.10.sup.-3 .times.V.sub.CE. The width W.sub.1 (.mu.m) of a portion of a second-conductivity-type isolation well that is close to the field insulating film on which the series Zener diode array is provided, and the width W.sub.2 (.mu.m) of a portion of the second-conductivity-type isolation well that is close to the field insulating film on which the series Zener diode array is not provided, are determined as a function of the clamp voltage V.sub.CE of the series Zener diode array, such that the widths W.sub.1, W.sub.2 are held in respective ranges as represented by: W.sub.1 .gtoreq.0.15 V.sub.CE, and W.sub.2 .gtoreq.0.05 V.sub.CE. By controlling the widths W.sub.1, W.sub.2 to these ranges, respectively, the concentration of current into an end portion of the cell portion of the device can be prevented upon cut-off of current from an inductive load.

摘要翻译： 提供一种MOS型半导体器件，其包括用于过电压保护的串联齐纳二极管阵列，其设置在源极区域和具有与漏极电极基本相同的电位的电极之间，以及场致绝缘膜，串联齐纳二极管阵列 提供。 确定场绝缘膜的厚度T（μm）作为串联齐纳二极管阵列的钳位电压VCE（V）的函数，使得厚度T保持在如下所示的范围内：T> / = 2.0x10-3xVCE。 第二导电型隔离阱的与串联齐纳二极管阵列的场绝缘膜接近的部分的宽度W1（μm）和宽度W2（μm） 靠近不具有串联齐纳二极管阵列的场绝缘膜的第二导电型隔离阱被确定为串联齐纳二极管阵列的钳位电压VCE的函数，使得宽度W1，W2 保持在各自的范围内，如：W1> / = 0.15VCE，W2> / = 0.05VCE。 通过分别将宽度W1，W2控制到这些范围，可以在从感性负载切断电流时，防止电流进入器件的电池部分端部的电流的浓度。

公开(公告)号：US5587655A

公开(公告)日：1996-12-24

申请号：US514208

申请日：1995-08-11

申请人： Kazunori Oyabe ,  Kazuhiko Yoshida ,  Tatsuhiko Fujihira

发明人： Kazunori Oyabe ,  Kazuhiko Yoshida ,  Tatsuhiko Fujihira

IPC分类号： G05F3/24 ,  G05F3/26 ,  G05F3/04 ,  G05F3/16

CPC分类号： G05F3/262 ,  Y10S323/907

摘要： A constant current circuit of the invention supplies a constant current to a load. The constant current circuit is formed of a current source device for providing an input current having a predetermined value with temperature dependence, a voltage divider device connected to the current source device, and an output transistor device. A reference transistor device or an adjusting transistor device is attached to the current source device. In case the reference transistor device is used, the voltage divider device divides a reference voltage of the reference transistor device to thereby generate a control voltage. In case the adjusting transistor device is used, an adjusting voltage from the voltage divider device is supplied to the adjusting transistor device to generate a control voltage. The output transistor device is connected to the load for controlling an output current supplied to the load in response to the control voltage. Temperature dependence of the output current is adjusted by setting voltage dividing ratio of the voltage divider device.

摘要翻译： 本发明的恒流电路向负载提供恒定电流。 恒流电路由电流源装置形成，用于提供具有温度依赖性的预定值的输入电流，连接到电流源装置的分压器件和输出晶体管器件。 参考晶体管器件或调节晶体管器件附接到电流源器件。 在使用参考晶体管器件的情况下，分压器器件分割参考晶体管器件的参考电压，从而产生控制电压。 在使用调节晶体管器件的情况下，来自分压器件的调节电压被提供给调节晶体管器件以产生控制电压。 输出晶体管器件连接到负载，用于响应于控制电压控制提供给负载的输出电流。 通过设定分压器的分压比来调节输出电流的温度依赖性。

公开(公告)号：US5399916A

公开(公告)日：1995-03-21

申请号：US978270

申请日：1992-11-18

申请人： Tatsuhiko Fujihira ,  Masaharu Nishiura

发明人： Tatsuhiko Fujihira ,  Masaharu Nishiura

IPC分类号： H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/088 ,  H03K3/01

CPC分类号： H01L27/088 ,  H01L27/0218

摘要： In a high-withstand-voltage integrated circuit, several circuits are included at different potentials. Each circuit of a different potential has a power source, and interface circuits mediate signals between the circuits of different potentials. By this design, the required number of high-withstand-voltage elements is reduced, and a low-cost, high-withstand-voltage IC with high integration density, surge tolerance and stability is obtained.

摘要翻译： 在高耐压集成电路中，包含不同电位的几个电路。 不同电位的每个电路具有电源，并且接口电路在不同电位的电路之间调停信号。 通过这种设计，可以减少所需数量的高耐压元件，并且获得具有高集成密度，浪涌耐受性和稳定性的低成本，高耐压IC。

公开(公告)号：US5319236A

公开(公告)日：1994-06-07

申请号：US913493

申请日：1992-07-14

申请人： Tatsuhiko Fujihira

发明人： Tatsuhiko Fujihira

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/40 ,  H01L27/02 ,  H01L29/68

CPC分类号： H01L29/1087 ,  H01L27/088 ,  H01L29/0615 ,  H01L29/1079 ,  H01L29/7835

摘要： The invention provides a semiconductor device equipped with a high-voltage MISFET capable of forming a push-pull circuit on one chip by optimizing a junction-separation structure. In an n-channel MOSFET, when a potential is applied to the gate electrode, to the source electrode, and across the drain electrode and the semiconductor substrate to expand the depletion layer from the junction face of a semiconductor substrate and a well formed thereon, the leading edge of the depletion layer does not reach a low-concentration drain diffusion region formed on the well. When a potential is applied to the drain electrode, to the semiconductor substrate, and across the source electrode and the gate electrode to expand a depletion layer from the junction face of the low-concentration drain diffusion region and the well, and a depletion layer from the junction face of semiconductor substrate and the well, the depletion layers are connected with each other.

摘要翻译： 本发明提供一种配备有能够通过优化结分离结构在一个芯片上形成推挽电路的高电压MISFET的半导体器件。 在n沟道MOSFET中，当向栅电极施加电位，并且在漏电极和半导体衬底两端施加电压以从半导体衬底的接合面和形成在其上的阱面扩大耗尽层时， 耗尽层的前沿未到达形成在阱上的低浓度漏极扩散区域。 当向漏电极，半导体衬底以及源极电极和栅极电极施加电位以从低浓度漏极扩散区域和阱的结面扩大耗尽层时， 半导体衬底的接合面和阱，耗尽层彼此连接。