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公开(公告)号:US12139569B2
公开(公告)日:2024-11-12
申请号:US17675055
申请日:2022-02-18
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Nazila Dadvand , Benjamin Stassen Cook , Archana Venugopal , Luigi Colombo
IPC: C08F292/00 , C08F8/42 , C08J5/00 , C08K3/04 , C08K3/08 , C08K7/00 , C08L25/06 , C08L33/12 , G03F1/78
Abstract: A method of forming a composite material includes photo-initiating a polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice. Unpolymerized monomer is removed from the polymer microlattice. The polymer microlattice is coated with a metal. The metal-coated polymer microlattice is dispersed in a polymer matrix.
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公开(公告)号:US11948871B2
公开(公告)日:2024-04-02
申请号:US17325197
申请日:2021-05-19
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Benjamin Stassen Cook , Yogesh Kumar Ramadass , Salvatore Frank Pavone , Mahmud Halim Chowdhury
IPC: H01L23/495 , H01L23/00
CPC classification number: H01L23/49589 , H01L23/4951 , H01L23/49524 , H01L24/32 , H01L24/73 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/92 , H01L2224/11462 , H01L2224/13147 , H01L2224/13564 , H01L2224/1357 , H01L2224/16245 , H01L2224/32265 , H01L2224/73203 , H01L2224/73253 , H01L2224/9211 , H01L2924/19015 , H01L2924/19041 , H01L2924/19103 , H01L2924/19104
Abstract: Disclosed embodiments include an integrated circuit (IC) comprising a silicon wafer, first and second conductive lines on the silicon wafer. There are first, second and third insulation blocks with portions on the first and second conductive lines and the silicon wafer, a metal pillar on the surface of the first conductive line opposite the silicon wafer, and a conductive adhesive block on the surface of the second conductive line opposite the silicon wafer. The IC also has a lead frame having first and second leads, and a capacitor having first and second capacitor terminals in which the first capacitor terminal is connected to the second lead using conductive adhesive, the second capacitor terminal is connected to the second conductive line through the conductive adhesive block, and the first lead is coupled to the first conductive line.
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公开(公告)号:US11869864B2
公开(公告)日:2024-01-09
申请号:US17679087
申请日:2022-02-24
Applicant: Texas Instruments Incorporated
Inventor: Benjamin Stassen Cook , Ralf Muenster , Sreenivasan Kalyani Koduri
IPC: H01L23/00 , H01L23/367 , H01L23/15 , H01L23/495 , H01L23/373
CPC classification number: H01L24/29 , H01L23/15 , H01L23/3677 , H01L23/3735 , H01L23/4951 , H01L23/49541 , H01L24/27 , H01L24/32 , H01L24/48 , H01L24/73 , H01L2224/2746 , H01L2224/29082 , H01L2224/29344 , H01L2224/29366 , H01L2224/29499 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48106 , H01L2224/48247 , H01L2224/73265 , H01L2924/2064
Abstract: In some examples, a system comprises a set of nanoparticles and a set of nanowires extending from the set of nanoparticles.
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公开(公告)号:US11854933B2
公开(公告)日:2023-12-26
申请号:US17138541
申请日:2020-12-30
Applicant: Texas Instruments Incorporated
Inventor: Benjamin Stassen Cook , Nazila Dadvand , Archana Venugopal , Daniel Lee Revier
IPC: H01L23/373 , H01L23/532 , H01L21/683 , H01L21/3205 , H01L21/78
CPC classification number: H01L23/373 , H01L21/32051 , H01L21/6835 , H01L21/78 , H01L23/53209
Abstract: In described examples, a semiconductor wafer with a thermally conductive surface layer comprises a bulk semiconductor layer having a first surface and a second surface, circuitry on the first surface, a metallic layer attached to the first surface or the second surface, and a graphene layer attached to the metallic layer. The first surface opposes the second surface. The metallic layer comprises a transition metal.
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公开(公告)号:US11728242B2
公开(公告)日:2023-08-15
申请号:US16843618
申请日:2020-04-08
Applicant: TEXAS INSTRUMENTS INCORPORATED
IPC: H01L23/48 , H01L21/768 , H01L23/495 , H01L23/00 , H01L21/288
CPC classification number: H01L23/481 , H01L21/76898 , H01L23/49575 , H01L24/32 , H01L24/33 , H01L24/73 , H01L21/2885 , H01L2224/32146 , H01L2224/73265
Abstract: In some examples, a semiconductor package comprises a semiconductor die having a first surface and a second surface opposing the first surface. The package comprises an orifice extending through a thickness of the semiconductor die from the first surface to the second surface. The package comprises a set of metallic nanowires positioned within the orifice and extending through the thickness of the semiconductor die from the first surface to the second surface.
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公开(公告)号:US11693235B2
公开(公告)日:2023-07-04
申请号:US17165895
申请日:2021-02-02
Applicant: Texas Instruments Incorporated
CPC classification number: G02B27/0006 , B08B7/028 , G01H13/00 , G01D5/2405
Abstract: An apparatus includes a mass detection circuit coupled to a surface covered with a plurality of electrodes. The mass detection circuit is configured to detect a mass of a first droplet present on the surface. The apparatus further includes a transducer circuit coupled to a transducer, which is coupled to the surface and form a lens unit. The transducer circuit configured to excite a first vibration of the surface at a resonant frequency to form a high displacement region on the surface. The apparatus also includes a voltage excitation circuit coupled to the plurality of electrodes. In response to the detection of the mass of the first droplet, the voltage excitation circuit is configured to apply a sequence of differential voltages on one or more consecutive electrodes which moves the first droplet to the high displacement region.
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公开(公告)号:US11607704B2
公开(公告)日:2023-03-21
申请号:US15492395
申请日:2017-04-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Abstract: Methods and apparatus for electrostatic control of expelled material for lens cleaners are disclosed. In certain described examples, an apparatus can expel fluid by atomization from a central area of the surface using an ultrasonic transducer mechanically coupled to the surface. A first electrode can be arranged relative to the central area of the surface. A second electrode can be located in a peripheral area relative to the central area of the surface, in which a voltage can be applied between the first and second electrodes to attract atomized fluid at the peripheral area.
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公开(公告)号:US20230059848A1
公开(公告)日:2023-02-23
申请号:US17828356
申请日:2022-05-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Scott Robert Summerfelt , Benjamin Stassen Cook , Simon Joshua Jacobs , Stefan Herzer
IPC: H01L23/48 , H01L25/065 , H01L21/768
Abstract: A device includes a die with a metallization stack. The device includes a substrate with a first region, a second region and a third region that underly the metallization stack and a first isolation trench filled with a polymer dielectric that extends between the first region and the second region of the substrate. The device also includes a second isolation trench filled with the polymer dielectric that extends between the second region and the third region. The polymer dielectric overlays a periphery of the substrate.
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公开(公告)号:US11522268B2
公开(公告)日:2022-12-06
申请号:US17116668
申请日:2020-12-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Hassan Omar Ali , Benjamin Stassen Cook
Abstract: A device comprises an integrated circuit (IC) die, a substrate, a printed circuit board (PCB), an antenna, and a waveguide stub. The IC die is affixed to the substrate, which comprises a signal launch on a surface of the substrate that is configured to emit or receive a signal. The substrate and the antenna are affixed to the PCB, such that the signal launch and a waveguide opening of the antenna are aligned and comprise a signal channel. The waveguide stub is arranged as a boundary around the signal channel. In some implementations, the waveguide stub has a height of λ/4, where λ represents a wavelength of the signal. In some implementations, the antenna includes the waveguide stub; in others, the substrate includes the waveguide stub.
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公开(公告)号:US20220375836A1
公开(公告)日:2022-11-24
申请号:US17325197
申请日:2021-05-19
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Benjamin Stassen Cook , Yogesh Kumar Ramadass , Salvatore Frank Pavone , Mahmud Halim Chowdhury
IPC: H01L23/495 , H01L23/00
Abstract: Disclosed embodiments include an integrated circuit (IC) comprising a silicon wafer, first and second conductive lines on the silicon wafer. There are first, second and third insulation blocks with portions on the first and second conductive lines and the silicon wafer, a metal pillar on the surface of the first conductive line opposite the silicon wafer, and a conductive adhesive block on the surface of the second conductive line opposite the silicon wafer. The IC also has a lead frame having first and second leads, and a capacitor having first and second capacitor terminals in which the first capacitor terminal is connected to the second lead using conductive adhesive, the second capacitor terminal is connected to the second conductive line through the conductive adhesive block, and the first lead is coupled to the first conductive line.
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