公开(公告)号：US11830769B2

公开(公告)日：2023-11-28

申请号：US17869337

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao Chang ,  Lin-Yu Huang ,  Li-Zhen Yu ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L21/768 ,  H01L21/76 ,  H01L23/528 ,  H01L23/532 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/06

CPC classification number: H01L21/7682 ,  H01L21/76 ,  H01L21/76834 ,  H01L23/5286 ,  H01L23/53295 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/78696 ,  H01L21/02172 ,  H01L21/02274 ,  H01L29/0673

Abstract: A semiconductor structure includes first and second source/drain (S/D) features, one or more semiconductor channel layers connecting the first and second S/D features, a gate structure engaging the one or more semiconductor channel layers, a metal wiring layer at a backside of the semiconductor structure, an S/D contact electrically connecting the first S/D feature to the metal wiring layer, and a seal layer between the metal wiring layer and the gate structure. The seal layer is spaced away from the gate structure by an air gap therebetween.

公开(公告)号：US20230369458A1

公开(公告)日：2023-11-16

申请号：US18355253

申请日：2023-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Shi Ning Ju ,  Kuan-Lun Cheng

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/775 ,  H01L29/165 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/088

CPC classification number: H01L29/6656 ,  H01L21/02532 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: A semiconductor device includes a plurality of nanostructures. The nanostructures each contain a semiconductive material. A plurality of first spacers circumferentially wrap around the nanostructures. A plurality of second spacers circumferentially wrap around the first spacers. A plurality of third spacers is disposed between the second spacers vertically. A gate structure surrounds the second spacers and the third spacers.

公开(公告)号：US20230369443A1

公开(公告)日：2023-11-16

申请号：US18358668

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien Ning Yao ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Wei-Yang Lee ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L21/3213

CPC classification number: H01L29/4991 ,  H01L29/66795 ,  H01L29/42364 ,  H01L29/41791 ,  H01L21/32135

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin formed on a substrate; and a gate structure disposed over a channel region of the semiconductor fin, the gate structure including a gate dielectric layer and a gate electrode, wherein the gate dielectric layer includes a bottom portion and a side portion, and the gate electrode is separated from the side portion of the gate dielectric layer by a first air gap.

公开(公告)号：US20230327025A1

公开(公告)日：2023-10-12

申请号：US18190754

申请日：2023-03-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching Wang ,  Jon-Hsu Ho ,  Wen-Hsing Hsieh ,  Kuan-Lun Cheng ,  Zhiqiang Wu

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/78696 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/6675 ,  H01L29/78645

Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary device includes a channel layer, a first source/drain feature, a second source/drain feature, and a metal gate. The channel layer has a first horizontal segment, a second horizontal segment, and a vertical segment connects the first horizontal segment and the second horizontal segment. The first horizontal segment and the second horizontal segment extend along a first direction, and the vertical segment extends along a second direction. The vertical segment has a width along the first direction and a thickness along the second direction, and the thickness is greater than the width. The channel layer extends between the first source/drain feature and the second source/drain feature along a third direction. The metal gate wraps channel layer. In some embodiments, the first horizontal segment and the second horizontal segment are nanosheets.

公开(公告)号：US20230307515A1

公开(公告)日：2023-09-28

申请号：US18328520

申请日：2023-06-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Wei Hsu ,  Lung-Kun Chu ,  Mao-Lin Huang ,  Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L29/786 ,  H01L29/423 ,  H01L21/8234

CPC classification number: H01L29/41733 ,  H01L29/78696 ,  H01L29/42392 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823412

Abstract: A semiconductor device includes a first interconnect structure and multiple channel layers stacked over the first interconnect structure. A bottommost one of the multiple channel layers is thinner than rest of the multiple channel layers. The semiconductor device further includes a gate stack wrapping around each of the channel layers except a bottommost one of the channel layers; a source/drain feature adjoining the channel layers; a first conductive via connecting the first interconnect structure to a bottom of the source/drain feature; and a dielectric feature under the bottommost one of the channel layers and directly contacting the first conductive via.

公开(公告)号：US11756959B2

公开(公告)日：2023-09-12

申请号：US17347218

申请日：2021-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Wei Tsai ,  Yu-Xuan Huang ,  Kuan-Lun Cheng ,  Wei Ju Lee ,  Chun-Fu Cheng ,  Chung-Wei Wu

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L21/265 ,  H01L21/266 ,  H01L21/74 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L27/0921 ,  H01L21/266 ,  H01L21/26513 ,  H01L21/74 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/42392 ,  H01L29/66537 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78696

Abstract: The present disclosure provides an integrated circuit that includes a circuit formed on a semiconductor substrate; and a de-cap device formed on the semiconductor substrate and integrated with the circuit. The de-cap device includes a filed-effect transistor (FET) that further includes a source and a drain connected through contact features landing on the source and drain, respectively; a gate stack overlying a channel and interposed between the source and the drain; and a doped feature disposed underlying the channel and connecting to the source and the drain, wherein the doped feature is doped with a dopant of a same type of the source and the drain.

公开(公告)号：US11742415B2

公开(公告)日：2023-08-29

申请号：US17178006

申请日：2021-02-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Shi Ning Ju ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/762 ,  H01L27/088 ,  H01L29/78 ,  H01L21/308

CPC classification number: H01L29/6681 ,  H01L21/3086 ,  H01L21/76224 ,  H01L27/0886 ,  H01L29/785

Abstract: FinFET patterning methods are disclosed for achieving fin width uniformity. An exemplary method includes forming a mandrel layer over a substrate. A first cut removes a portion of the mandrel layer, leaving a mandrel feature disposed directly adjacent to a dummy mandrel feature. The substrate is etched using the mandrel feature and the dummy mandrel feature as an etch mask, forming a dummy fin feature and an active fin feature separated by a first spacing along a first direction. A second cut removes a portion of the dummy fin feature and a portion of the active fin feature, forming dummy fins separated by a second spacing and active fins separated by the second spacing. The second spacing is along a second direction substantially perpendicular to the first direction. A third cut removes the dummy fins, forming fin openings, which are filled with a dielectric material to form dielectric fins.

公开(公告)号：US11735594B2

公开(公告)日：2023-08-22

申请号：US17341142

申请日：2021-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzer-Min Shen ,  Zhiqiang Wu ,  Chung-Cheng Wu ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang ,  Min Cao

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/786 ,  H01L27/12 ,  H01L21/762 ,  H01L21/84 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L29/04

CPC classification number: H01L27/1207 ,  H01L21/76275 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/785 ,  H01L29/7869 ,  H01L21/823878 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/7853

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a crystalline direction along the first direction.

公开(公告)号：US11735587B2

公开(公告)日：2023-08-22

申请号：US17510014

申请日：2021-10-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Xuan Huang ,  Ching-Wei Tsai ,  Jam-Wem Lee ,  Kuo-Ji Chen ,  Kuan-Lun Cheng

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/417 ,  H01L29/06 ,  H01L27/07 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L27/0727 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: The present disclosure provides embodiments of semiconductor devices. A semiconductor device according to the present disclosure include an elongated semiconductor member surrounded by an isolation feature and extending lengthwise along a first direction, a first source/drain feature and a second source/drain feature over a top surface of the elongated semiconductor member, a vertical stack of channel members each extending lengthwise between the first source/drain feature and the second source/drain feature along the first direction, a gate structure wrapping around each of the channel members, an epitaxial layer deposited on the bottom surface of the elongated semiconductor member, a silicide layer disposed on the epitaxial layer, and a conductive layer disposed on the silicide layer.

公开(公告)号：US11699742B2

公开(公告)日：2023-07-11

申请号：US17199877

申请日：2021-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Kuan-Lun Cheng

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/66795 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/7851

Abstract: A method includes providing a structure having a frontside and a backside, the structure including a substrate, two or more semiconductor channel layers over the substrate and connecting a first source/drain (S/D) feature and a second S/D feature, and a gate structure engaging the semiconductor channel layers, wherein the substrate is at the backside of the structure and the gate structure is at the frontside of the structure; recessing the first S/D feature, thereby exposing a terminal end of one of the semiconductor channel layers; and depositing a dielectric layer on the first S/D feature and covering the exposed terminal end of the one of the semiconductor channel layers.