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155 条记录 (耗时 0.031 秒)

    Structure/method to fabricate a high performance magnetic tunneling junction MRAM
    91.
    发明授权
    Structure/method to fabricate a high performance magnetic tunneling junction MRAM 失效
    制造高性能磁隧道结MRAM的结构/方法

    公开(公告)号：US07122852B2

    公开(公告)日：2006-10-17

    申请号：US10844171

    申请日：2004-05-12

    申请人： Cheng T. Horng ,  Mao-Min Chen ,  Liubo Hong ,  Ru-Ying Tong

    发明人： Cheng T. Horng ,  Mao-Min Chen ,  Liubo Hong ,  Ru-Ying Tong

    IPC分类号： H01L31/113 ,  H01L29/76 ,  H01L21/00

    CPC分类号： H01L43/12 ,  H01L43/08 ,  Y10S977/934 ,  Y10S977/935

    摘要： An MTJ (magnetic tunneling junction) MRAM (magnetic random access memory) cell is formed on a conducting lead and magnetic keeper layer that is capped by a sputter-etched Ta layer. The Ta layer has a smooth surface as a result of the sputter-etching and that smooth surface promotes the subsequent formation of a lower electrode (pinning/pinned layer) with smooth, flat layers and a radical oxidized (ROX) Al tunneling barrier layer which is ultra-thin, smooth, and to has a high breakdown voltage. A seed layer of NiCr is formed on the sputter-etched layer of Ta. The resulting device has generally improved performance characteristics in terms of its switching characteristics, GMR ratio and junction resistance.

    摘要翻译： 在由溅射蚀刻的Ta层覆盖的导电引线和磁保持层上形成MTJ（磁性隧道结）MRAM（磁性随机存取存储器）单元。 作为溅射蚀刻的结果，Ta层具有光滑的表面，并且光滑的表面促进随后形成具有光滑的平坦层和自由基氧化（ROX）Al隧穿势垒层的下电极（钉扎/钉扎层），其中 具有超薄，光滑，且具有较高的击穿电压。 在Ta的溅射蚀刻层上形成NiCr种子层。 在其开关特性，GMR比和结电阻方面，所得到的器件通常具有改进的性能特性。

    Giant magnetoresistive (GMR) sensor element with enhanced magnetoresistive (MR) coefficient
    96.
    发明授权
    Giant magnetoresistive (GMR) sensor element with enhanced magnetoresistive (MR) coefficient 失效
    具有增强磁阻（MR）系数的巨磁阻（GMR）传感器元件

    公开(公告)号：US06292336B1

    公开(公告)日：2001-09-18

    申请号：US09408703

    申请日：1999-09-30

    申请人： Cheng T. Horng ,  Ru-Ying Tong ,  Kochan Ju ,  Mao-Min Chen ,  Jei-Wei Chang ,  Simon H. Liao

    发明人： Cheng T. Horng ,  Ru-Ying Tong ,  Kochan Ju ,  Mao-Min Chen ,  Jei-Wei Chang ,  Simon H. Liao

    IPC分类号： G11B5127

    CPC分类号： B82Y25/00 ,  B82Y10/00 ,  G01R33/093 ,  G11B5/3903 ,  G11B5/3967 ,  G11B2005/3996 ,  H01F10/3268

    摘要： A method for forming a giant magnetoresistive (GMR) sensor element, and a giant magnetoresistive (GMR) sensor element formed in accord with the method. In accord with the method, there is first provided a substrate. There is then formed over the substrate a seed layer formed of a magnetoresistive (MR) resistivity sensitivity enhancing material selected from the group consisting or nickel-chromium alloys and nickel-iron-chromium alloys. There is then formed over the seed layer a nickel oxide material layer. Finally, there is then formed over the nickel oxide material layer a free ferromagnetic layer separated from a pinned ferromagnetic layer in turn formed thereover by a non-magnetic conductor spacer layer, where the pinned ferromagnetic layer in turn has a pinning material layer formed thereover. The method contemplates a giant magnetoresistive (GMR) sensor element formed in accord with the method. The nickel oxide material layer provides the giant magnetoresistive (GMR) sensor element with an enhanced magnetoresistive (MR) resistivity sensitivity.

    摘要翻译： 一种用于形成巨磁阻（GMR）传感器元件的方法，以及根据该方法形成的巨磁阻（GMR）传感元件。 根据该方法，首先提供基板。 然后在衬底上形成由选自镍铬合金和镍 - 铁 - 铬合金的磁阻（MR）电阻率敏感度增强材料形成的晶种层。 然后在种子层上形成氧化镍材料层。 最后，然后在氧化镍材料层上形成与被钉扎的铁磁性层分离的自由铁磁层，然后由非磁性导体间隔层形成，其中钉扎的铁磁层又形成有钉扎材料层。 该方法考虑了根据该方法形成的巨磁阻（GMR）传感器元件。 氧化镍材料层提供具有增强的磁阻（MR）电阻率敏感性的巨磁阻（GMR）传感器元件。

    Method of fabrication of striped magnetoresistive (SMR) and dual stripe magnetoresistive (DSMR) heads with anti-parallel exchange configuration
    97.
    发明授权
    Method of fabrication of striped magnetoresistive (SMR) and dual stripe magnetoresistive (DSMR) heads with anti-parallel exchange configuration 失效
    具有反并联交换配置的带状磁阻（SMR）和双条磁阻（DSMR）头的制造方法

    公开(公告)号：US06204071B1

    公开(公告)日：2001-03-20

    申请号：US09408491

    申请日：1999-09-30

    申请人： Kochan Ju ,  Mao-Min Chen ,  Cheng T. Horng ,  Jei-Wei Chang

    发明人： Kochan Ju ,  Mao-Min Chen ,  Cheng T. Horng ,  Jei-Wei Chang

    IPC分类号： H01L2100

    CPC分类号： B82Y25/00 ,  B82Y10/00 ,  G11B5/3163 ,  G11B5/3903 ,  G11B5/3932 ,  G11B5/3948 ,  G11B2005/3996

    摘要： A method for forming a longitudinally magnetically biased dual stripe magnetoresistive (DSMR) sensor element comprises forming a first patterned magnetoresistive (MR) layer. Contact the opposite ends of the patterned magnetoresistive (MR) layer with a first pair of stacks defining a track width of the first magnetoresistive (MR) layer, each of the stacks including a first Anti-Ferro-Magnetic (AFM) layer and a first lead layer. Then anneal the device in the presence of a longitudinal external magnetic field. Next, form a second patterned magnetoresistive (MR) layer above the previous structure. Contact the opposite ends of the second patterned magnetoresistive (MR) layer with a second pair of stacks defining a second track width of the second patterned magnetoresistive (MR) layer. Each of the second pair of stacks includes spacer layer composed of a metal, a Ferro-Magnetic (FM) layer, a second Anti-Ferro-Magnetic (AFM) layer and a second lead layer. Then anneal the device in the presence of a second longitudinal external magnetic field.

    摘要翻译： 用于形成纵向磁偏置双条磁阻（DSMR）传感器元件的方法包括形成第一图案化磁阻（MR）层。 用限定第一磁阻（MR）层的轨道宽度的第一对叠层接触图案化磁阻（MR）层的相对端，每个堆叠包括第一抗铁磁（AFM）层和第一 铅层。 然后在存在纵向外部磁场的情况下退火该器件。 接下来，在先前的结构之上形成第二图案化磁阻（MR）层。 用限定第二图案化磁阻（MR）层的第二磁道宽度的第二对叠层接触第二图案化磁阻（MR）层的相对端。 第二对堆叠中的每一个包括由金属，铁磁（FM）层，第二抗铁磁（AFM）层和第二引线层组成的间隔层。 然后在存在第二纵向外部磁场的情况下退火该器件。

    Process for fabricating a bipolar transistor
    99.
    发明授权
    Process for fabricating a bipolar transistor 失效
    制造双极晶体管的工艺

    公开(公告)号：US4338138A

    公开(公告)日：1982-07-06

    申请号：US126611

    申请日：1980-03-03

    申请人： Joseph R. Cavaliere ,  Cheng T. Horng ,  Richard R. Konian ,  Hans S. Rupprecht ,  Robert O. Schwenker

    发明人： Joseph R. Cavaliere ,  Cheng T. Horng ,  Richard R. Konian ,  Hans S. Rupprecht ,  Robert O. Schwenker

    IPC分类号： H01L21/8222 ,  H01L21/033 ,  H01L21/285 ,  H01L21/331 ,  H01L21/762 ,  H01L27/06 ,  H01L29/73 ,  H01L29/732 ,  H01L21/263 ,  H01L21/203 ,  H01L21/22 ,  H01L21/31

    CPC分类号： H01L29/66272 ,  H01L21/033 ,  H01L21/28525 ,  H01L21/76229 ,  H01L21/76232 ,  H01L29/7325 ,  Y10S148/131

    摘要： An improved bipolar transistor structure formed in a very small area of a thin epitaxial layer on a planar surface of a silicon substrate of first conductivity type, said very small area of the thin epitaxial layer having vertical sidewalls extending to the planar surface of said substrate, said area of thin epitaxial layers containing in the order recited a shallow depth emitter region of a second conductivity type having an exposed planar surface, a shallow depth base region of said first conductivity type, and a shallow depth active collector region of said second conductivity type, an elongated region of said first conductivity type surrounding said emitter, base and active collector regions, said elongated region being contained within and coextensive with said vertical sidewalls of said small area of said thin epitaxial layer, whereby the base collector capacitance is materially reduced due to the very small area of the base-collector junction. Also disclosed is a process and alternative process, for fabricating an improved bipolar transistor structure.

    摘要翻译： 一种改进的双极晶体管结构，其形成在第一导电类型的硅衬底的平坦表面上的薄外延层的非常小的区域中，所述薄外延层的非常小的面积具有延伸到所述衬底的平坦表面的垂直侧壁， 所述薄外延层的区域包含按顺序列出的具有暴露平面的第二导电类型的浅深度发射极区域，所述第一导电类型的浅深度基底区域和所述第二导电类型的浅深度有源集电极区域 围绕所述发射极，基极和主动集电极区域的所述第一导电类型的细长区域，所述细长区域包含在所述薄外延层的所述小区域的所述垂直侧壁内并与之共同延伸，由此基极集电极电容由于 到基极 - 集电极结的非常小的区域。 还公开了用于制造改进的双极晶体管结构的工艺和替代工艺。

    High performance bipolar transistors fabricated by post emitter base implantation process
    100.
    发明授权
    High performance bipolar transistors fabricated by post emitter base implantation process 失效
    通过后发射极基极注入工艺制造的高性能双极晶体管

    公开(公告)号：US4242791A

    公开(公告)日：1981-01-06

    申请号：US77699

    申请日：1979-09-21

    申请人： Cheng T. Horng ,  Harold V. Lillja ,  David K. Seto

    发明人： Cheng T. Horng ,  Harold V. Lillja ,  David K. Seto

    IPC分类号： H01L29/73 ,  H01L21/033 ,  H01L21/266 ,  H01L21/316 ,  H01L21/331 ,  H01L21/76 ,  H01L29/10 ,  B01J17/00

    CPC分类号： H01L29/1004 ,  H01L21/033 ,  H01L21/31687 ,  Y10S148/131

    摘要： Disclosed is a method for fabricating very high performance semiconductor devices, particularly bipolar-type transistors having a heavily doped inactive base and a lightly doped narrow active base formed by ion implantation. In order to prevent the high dose boron implantation, for an NPN transistor, from getting into the active base region, a self-aligned mask covering the emitter contact i.e., active base region, is required for inactive base implantation. The self-aligned mask is anodically oxidized aluminum pads. The device wafer metallized with blanket aluminum film is immersed in a dilute H.sub.2 SO.sub.4 solution electrolytic cell which selectively anodizes only the aluminum lands situated over the Si.sub.3 N.sub.4 /SiO.sub.2 defined device contact windows. The aluminum oxide formed by anodization process is porous but may be sealed and densified. The aluminum film that is not anodized is then selectively etched off using either chemical solution or sputter etching. Using the aluminum oxide formed over the contact windows to mask the active base region, a high dose boron implantation is made through the Si.sub.3 N.sub.4 /SiO.sub.2 layers to dope the external base region. After stripping the aluminum oxide from the emitter contact window, the emitter with a desired concentration profile and junction depth is subsequently formed. Formation of the active base is formed by a low dose boron implantation made with its concentration peak below the emitter. A relatively low temperature annealing, as for example, 900.degree. C., is used to fully activate the implanted boron and minimize the redistribution of the active base doping profile. The device thus formed will have a controllable narrow base width and doping profile.

    摘要翻译： 公开了一种用于制造非常高性能的半导体器件的方法，特别是具有重掺杂非活性碱和通过离子注入形成的轻掺杂窄活性碱的双极型晶体管。 为了防止对于NPN晶体管的高剂量硼注入进入有源基极区域，需要一个覆盖发射极接触的自对准掩模，即有源基极区域，用于无源基极植入。 自对准掩模是阳极氧化铝垫。 用橡皮布铝膜金属化的器件晶片浸入稀释的H 2 SO 4溶液电解池中，该电解池仅选择性地阳极氧化位于Si 3 N 4 / SiO 2界定的器件接触窗上方的铝焊盘。 通过阳极氧化法形成的氧化铝是多孔的，但可以被密封和致密化。 然后使用化学溶液或溅射蚀刻选择性地蚀刻掉未阳极氧化的铝膜。 使用形成在接触窗口上的氧化铝来掩蔽活性碱性区域，通过Si 3 N 4 / SiO 2层制备高剂量硼注入以掺杂外部碱性区域。 在从发射极接触窗口剥离氧化铝之后，随后形成具有所需浓度分布和结深度的发射极。 活性碱的形成是通过低浓度硼掺杂形成的，其浓度峰值低于发射极。 使用相对低温退火（例如900℃）来完全激活注入的硼并最小化活性碱掺杂分布的再分配。 如此形成的器件将具有可控的窄基极宽度和掺杂分布。