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    Surface treatment to improve resistive-switching characteristics
    93.
    发明授权
    Surface treatment to improve resistive-switching characteristics 有权
    表面处理提高电阻开关特性

    公开(公告)号：US08872151B2

    公开(公告)日：2014-10-28

    申请号：US13896955

    申请日：2013-05-17

    Applicant: Intermolecular Inc.

    Inventor： Michael Miller ,  Tony P. Chiang ,  Xiying Costa ,  Tanmay Kumar ,  Prashant B Phatak ,  April Schricker

    IPC: H01L29/02 ,  H01L47/00

    CPC classification number: H01L45/16 ,  H01L21/265 ,  H01L21/31155 ,  H01L27/2463 ,  H01L29/8615 ,  H01L45/08 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/165

    Abstract: This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.

    Abstract translation: 本公开提供了制造半导体器件层和相关联的存储单元结构的方法。 通过进行半导体器件层的表面处理（例如离子轰击）以产生具有有意深度分布的缺陷，可以创建具有更一致的电参数的多层存储单元。 例如，在电阻式开关存储单元中，可以获得设定和复位电压的更紧密的分配和较低的成形电压，从而提高器件的产量和可靠性。 在至少一个实施例中，选择深度轮廓以调制缺陷的类型及其对被轰击的金属氧化物层的电性能的影响并增强均匀的缺陷分布。

    Screening of Surface Passivation Processes for Germanium Channels
    94.
    发明申请
    Screening of Surface Passivation Processes for Germanium Channels 审中-公开
    锗通道表面钝化过程的筛选

    公开(公告)号：US20140315331A1

    公开(公告)日：2014-10-23

    申请号：US14205078

    申请日：2014-03-11

    Applicant: Intermolecular, Inc.

    Inventor： Sandip Niyogi ,  Shuogang Huang ,  Chi-I Lang

    IPC: H01L21/66 ,  H01L21/306

    CPC classification number: H01L22/12 ,  H01L21/02052 ,  H01L21/306 ,  H01L21/30604 ,  H01L21/67051 ,  H01L21/6708 ,  H01L22/20 ,  H01L22/26

    Abstract: Candidate wet processes for native oxide removal from, and passivation of, germanium surfaces can be screened by high-productivity combinatorial variation of different process parameters on different site-isolated regions of a single substrate. Variable process parameters include the choice of hydrohalic acid used to remove the native oxide, the concentration of the acid in the solution, the exposure time, and the use of an optional sulfur passivation step. Measurements to compare the results of the process variations include attenuated total reflectance Fourier transform infrared spectroscopy (ATR-FTIR), contact angle, atomic force microscopy (AFM), scanning electron microscopy (SEM), and X-ray fluorescence (XRF). A sample screening experiment indicated somewhat less native oxide regrowth using HCl or HBr without sulfur passivation, compared to using HF with sulfur passivation.

    Abstract translation: 可以通过在单个衬底的不同位置分离区域上的不同工艺参数的高生产率组合变化来筛选锗表面的自然氧化物去除和钝化的候选湿法。 可变工艺参数包括用于去除天然氧化物的氢卤酸的选择，溶液中酸的浓度，暴露时间以及使用任选的硫钝化步骤。 用于比较过程变化结果的测量包括衰减全反射傅立叶变换红外光谱（ATR-FTIR），接触角，原子力显微镜（AFM），扫描电子显微镜（SEM）和X射线荧光（XRF）。 与使用具有硫钝化的HF相比，样品筛选实验表明使用没有硫钝化的HCl或HBr较少的天然氧化物再生长。

    Counter-doped low-power FinFET
    97.
    发明授权
    Counter-doped low-power FinFET 有权
    反掺杂低功耗FinFET

    公开(公告)号：US08853008B1

    公开(公告)日：2014-10-07

    申请号：US13871270

    申请日：2013-07-15

    Applicant: Intermolecular, Inc.

    Inventor： Mankoo Lee

    IPC: H01L21/332 ,  H01L29/76 ,  H01L21/265 ,  H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/785 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/165 ,  H01L29/66803 ,  H01L29/7848

    Abstract: FinFETs and methods for making FinFETs are disclosed. A fin is formed on a substrate, wherein the fin has a height greater than 2 to 6 times of its width, a length defining a channel between source and drain ends, and the fin comprises a lightly doped semiconductor. A conformally doped region of counter-doped semiconductor is formed on the fin using methods such as monolayer doping, sacrificial oxide doping, or low energy plasma doping. Halo-doped regions are formed by angled ion implantation. The halo-doped regions are disposed in the lower portion of the source and drain and adjacent to the fin. Energy band barrier regions can be formed at the edges of the halo-doped regions by angled ion implantation.

    Abstract translation: FinFET和FinFET的制造方法被公开。 散热片形成在基板上，其中散热片具有高于其宽度的2至6倍的高度，限定源极和漏极端之间的通道的长度，并且散热片包括轻掺杂半导体。 使用诸如单层掺杂，牺牲氧化物掺杂或低能量等离子体掺杂的方法在翅片上形成反掺杂半导体的保形掺杂区域。 通过成角度离子注入形成光晕掺杂区域。 卤素掺杂区域设置在源极和漏极的下部并且与鳍片相邻。 可以通过成角度的离子注入在卤素掺杂区域的边缘处形成能带阻挡区域。

    Carbon doped resistive switching layers
    98.
    发明授权
    Carbon doped resistive switching layers 有权
    碳掺杂电阻开关层

    公开(公告)号：US08852996B2

    公开(公告)日：2014-10-07

    申请号：US13721587

    申请日：2012-12-20

    Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

    Inventor： Yun Wang ,  Tony P. Chiang ,  Tim Minvielle ,  Takeshi Yamaguchi

    IPC: H01L29/02 ,  H01L45/00

    CPC classification number: H01L45/1633 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1641

    Abstract: Provided are carbon doped resistive switching layers, resistive random access memory (ReRAM) cells including these layers, as well as methods of forming thereof. Carbon doping of metal containing materials creates defects in these materials that allow forming and breaking conductive paths as evidenced by resistive switching. Relative to many conventional dopants, carbon has a lower diffusivity in many suitable base materials. As such, these carbon doped materials exhibit structural stability and consistent resistive switching over many operating cycles. Resistive switching layers may include as much as 30 atomic percent of carbon, making the dopant control relatively simple and flexible. Furthermore, carbon doping has acceptor characteristics resulting in a high resistivity and low switching currents, which are very desirable for ReRAM applications. Carbon doped metal containing layer may be formed from metalorganic precursors at temperatures below saturation ranges of atomic layer deposition.

    Abstract translation: 提供碳掺杂电阻开关层，包括这些层的电阻随机存取存储器（ReRAM）单元以及其形成方法。 含金属材料的碳掺杂在这些材料中产生缺陷，允许形成和断开导电路径，如电阻式开关所证明的。 相对于许多常规掺杂剂，碳在许多合适的基材中具有较低的扩散系数。 因此，这些碳掺杂材料在许多操作循环中表现出结构稳定性和一致的电阻切换。 电阻开关层可以包括多达30原子％的碳，使得掺杂剂控制相对简单和灵活。 此外，碳掺杂具有导致高电阻率和低开关电流的受体特性，这对于ReRAM应用是非常需要的。 含碳掺杂金属的层可以在低于原子层沉积的饱和范围的温度下由金属有机前体形成。

    Dissolution rate monitor
    99.
    发明授权
    Dissolution rate monitor 有权
    溶出率监测

    公开(公告)号：US08852967B2

    公开(公告)日：2014-10-07

    申请号：US13721534

    申请日：2012-12-20

    Applicant: Intermolecular, Inc.

    Inventor： George Mirth

    IPC: H01L21/66 ,  C23F1/00 ,  H01L21/67

    CPC classification number: H01L21/67063 ,  H01L21/6708 ,  H01L21/67126 ,  H01L21/6719 ,  H01L21/68771 ,  H01L22/12 ,  H01L22/26

    Abstract: A multiple channel site-isolated reactor system and method are described. The system contains a reactor block with a plurality of reactors. Input lines are coupled to each reactor to provide a fluid to the respective reactors. A sealing element associated with each reactor contacts a surface of a substrate disposed below the reactor block, which defines isolated regions on the surface of the substrate. A dissolution rate monitor extends into each reactor to monitor a rate of real-time dissolution of one or more layers on the surface of the substrate when it is disposed proximate to the surface of the substrate.

    Abstract translation: 描述了多通道位置分离的反应器系统和方法。 该系统包含具有多个反应器的反应器块。 输入线连接到每个反应器以向相应的反应器提供流体。 与每个反应器相关联的密封元件接触设置在反应器块下方的基板的表面，其限定了基板表面上的隔离区域。 溶解速率监测器延伸到每个反应器中，以便当它靠近衬底的表面设置时，监测衬底表面上的一个或多个层的实时溶解的速率。

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