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    Termination circuits and semiconductor memory devices having the same
    101.
    发明申请
    Termination circuits and semiconductor memory devices having the same 有权
    终端电路和具有该终端电路的半导体存储器件

    公开(公告)号：US20070205848A1

    公开(公告)日：2007-09-06

    申请号：US11649805

    申请日：2007-01-05

    Applicant: Kwang-Soo Park ,  Jae-Jun Lee ,  Jong-Hoon Kim ,  Hoe-Ju Chung

    Inventor： Kwang-Soo Park ,  Jae-Jun Lee ,  Jong-Hoon Kim ,  Hoe-Ju Chung

    IPC: H01P5/12 ,  H03H7/38

    CPC classification number: H03H7/38

    Abstract: A termination circuit is connected to an input buffer receiving a data signal, and includes at least one termination resistor connected to the input buffer for impedance matching. At least one switch controls a connection between the input buffer and a corresponding one of the at least one termination resistors. A control signal generator generates a control signal for selectively enabling the termination circuit by controlling each of the at least one switches. The control signal has an input period less than or equal to an input period of a data signal.

    Abstract translation: 终端电路连接到接收数据信号的输入缓冲器，并且包括连接到输入缓冲器以用于阻抗匹配的至少一个终端电阻器。 至少一个开关控制输入缓冲器与至少一个终端电阻器中相应的一个之间的连接。 控制信号发生器产生控制信号，用于通过控制至少一个开关中的每个开关来选择性地启用终端电路。 控制信号的输入周期小于或等于数据信号的输入周期。

    Semiconductor memory device with data bus scheme for reducing high frequency noise
    105.
    发明授权
    Semiconductor memory device with data bus scheme for reducing high frequency noise 有权
    具有数据总线方案的半导体存储器件，用于降低高频噪声

    公开(公告)号：US07239216B2

    公开(公告)日：2007-07-03

    申请号：US10424923

    申请日：2003-04-29

    Applicant: Myun-Joo Park ,  Jae-Jun Lee

    Inventor： Myun-Joo Park ,  Jae-Jun Lee

    IPC: H01P5/12

    CPC classification number: H05K1/0216 ,  G11C7/1006 ,  H05K1/0237 ,  H05K1/14 ,  H05K2201/044 ,  H05K2201/09727 ,  H05K2201/09781

    Abstract: A semiconductor memory device includes memory modules which have memories and a data bus which transfers data to the memory modules, in which the data bus comprises a low frequency band data pass unit which removes the high frequency component of the data and sends the data to the memory modules. The low frequency band data pass unit comprises a plurality of stubs which are connected to the data bus in parallel and are formed as printed circuit board (PCB) patterns. The low frequency band data pass unit comprises a plurality of plates that are connected to the data bus in parallel and are formed as PCB patterns. The low frequency band data pass unit has a shape in which parts having a wide width and parts having a narrow width are alternately connected. Therefore, without adding a separate passive device, the semiconductor memory device reduces the high frequency noise of data transferred through a data bus such that the voltage margin of the data improves, the cost for passive devices such as capacitors, is reduced, and the process for attaching the passive devices is simplified.

    Abstract translation: 半导体存储器件包括具有存储器的存储器模块和将数据传送到存储器模块的数据总线，其中数据总线包括低频带数据传递单元，该单元去除数据的高频分量并将数据发送到 内存模块 低频带数据传送单元包括并联连接到数据总线并形成为印刷电路板（PCB）图案的多个短截线。 低频带数据传送单元包括并联连接到数据总线并形成为PCB图案的多个板。 低频带数据传送单元具有宽度宽的部分和宽度窄的部分交替连接的形状。 因此，在不添加单独的无源器件的情况下，半导体存储器件减少通过数据总线传送的数据的高频噪声，从而数据的电压裕度提高，诸如电容器等无源器件的成本降低，并且该过程 用于安装无源器件简化了。

    Memory system having point-to-point (PTP) and point-to-two-point (PTTP) links between devices
    106.
    发明申请
    Memory system having point-to-point (PTP) and point-to-two-point (PTTP) links between devices 有权
    在设备之间具有点到点（PTP）和点到两点（PTTP）链路的存储器系统

    公开(公告)号：US20070133247A1

    公开(公告)日：2007-06-14

    申请号：US11603648

    申请日：2006-11-22

    Applicant: Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

    Inventor： Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

    IPC: G11C5/06

    CPC classification number: G11C5/063

    Abstract: A memory system has first and second primary memories and first and second secondary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection. A memory module includes at least two of the first and second primary and first and second secondary memories. A first connection element, such as a connector or solder, connects the memory module to a mother board. A second connection element, such as a connector or solder, connects at least one other of the first and second primary and first and second secondary memories to the mother board. At least one of the memories on the first memory module is coupled to at least one of the other memories. The memory system also includes a memory controller which is connected to the primary memories by a point-to-two-point link.

    Abstract translation: 存储器系统具有第一和第二主存储器以及分别耦合到第一和第二主存储器的第一和第二辅助存储器，耦合器包括至少一个点到点连接。 存储器模块包括第一和第二主要和第一和第二辅助存储器中的至少两个。 诸如连接器或焊料的第一连接元件将存储器模块连接到母板。 诸如连接器或焊料的第二连接元件将第一和第二初级和第二和第二辅助存储器中的至少一个连接到母板。 第一存储器模块上的至少一个存储器耦合到至少一个其他存储器。 存储器系统还包括存储器控制器，其通过点对二点链接连接到主存储器。

    Ion-conducting crosslinked copolymer and fuel cell comprising the same
    108.
    发明申请
    Ion-conducting crosslinked copolymer and fuel cell comprising the same 有权
    离子导电交联共聚物和包含其的燃料电池

    公开(公告)号：US20070082247A1

    公开(公告)日：2007-04-12

    申请号：US11546779

    申请日：2006-10-11

    Applicant: Jae-jun Lee ,  Jin-gyu Lee ,  Sang-kook Mah ,  Myung-sup Jung

    Inventor： Jae-jun Lee ,  Jin-gyu Lee ,  Sang-kook Mah ,  Myung-sup Jung

    IPC: H01M8/10 ,  C08J5/20 ,  C08G75/00

    CPC classification number: C08G65/4056 ,  C08J5/2256 ,  C08J2371/12 ,  H01B1/122 ,  H01M8/04186 ,  H01M8/1011 ,  H01M8/1246 ,  H01M2300/0082 ,  Y02E60/523 ,  Y02E60/525 ,  Y02P70/56

    Abstract: An ion-conducting, sulfonated and crosslinked copolymer for use in a fuel cell is disclosed. The ion-conducting, sulfonated and crosslinked copolymer is made up of four monomers. The first monomer is an aromatic diol. The second monomer includes two groups, each group capable of reacting with the hydroxy groups of the first monomer, and each group independently selected from a nitro group and a halogen group. The third monomer is one of the first monomer or the second monomer, except that one of the hydrogen atoms attached to a benzene ring is substituted with —SO3Y, where Y is selected from hydrogen (H), lithium (Li), sodium (Na), potassium (K) and trialkyl ammonium of the form HNR3 where R is an alkyl group having from 1 to 5 carbon atoms. The fourth monomer includes at least three groups, each independently selected from a hydroxy group, a nitro group, and a halogen group.

    Abstract translation: 公开了一种用于燃料电池的离子导电磺化交联共聚物。 离子导电，磺化和交联的共聚物由四种单体组成。 第一单体是芳族二醇。 第二单体包括两个基团，每个基团能够与第一单体的羟基反应，每个基团独立地选自硝基和卤素基团。 第三单体是第一单体或第二单体之一，除了连接到苯环的一个氢原子被-SO 3 Y取代，其中Y选自氢（H） ，锂（Li），钠（Na），钾（K）和HNR 3 N 3的三烷基铵，其中R是具有1至5个碳原子的烷基。 第四单体包括至少三个基团，各自独立地选自羟基，硝基和卤素基团。

    Memory system including on-die termination unit having inductor
    110.
    发明申请
    Memory system including on-die termination unit having inductor 有权
    存储器系统包括具有电感器的片上终端单元

    公开(公告)号：US20070030024A1

    公开(公告)日：2007-02-08

    申请号：US11377665

    申请日：2006-03-17

    Applicant: Jae-Jun Lee ,  Kwang-Soo Park

    Inventor： Jae-Jun Lee ,  Kwang-Soo Park

    IPC: H03K17/16

    CPC classification number: G11C7/1051 ,  G11C5/14 ,  G11C7/1057 ,  H04L25/0278 ,  H04L25/0298

    Abstract: Provided is a memory system with an inductor. In the memory system, the inductor is connected to an on-die termination unit of a memory chip, thereby realizing constant gain characteristics without respect to a variation in an operating frequency. The inductor of the on-die termination unit may be embodied by connecting a wire bonding, a package line pattern, a PCB line pattern, a wire line, and/or an inductor device to pads of the memory chip.

    Abstract translation: 提供了具有电感器的存储器系统。 在存储器系统中，电感器连接到存储器芯片的片上终端单元，从而实现恒定的增益特性而不考虑工作频率的变化。 可以通过将引线接合，封装线图案，PCB线图案，有线线路和/或电感器件连接到存储器芯片的焊盘来实现片上端接单元的电感器。

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